src/arch/power/isa.hh

   1 /*
   2  * Copyright (c) 2009 The Regents of The University of Michigan
   3  * Copyright (c) 2009 The University of Edinburgh
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #ifndef __ARCH_POWER_ISA_HH__
  31 #define __ARCH_POWER_ISA_HH__
  32
  33 #include "arch/generic/isa.hh"
  34 #include "arch/power/registers.hh"
  35 #include "arch/power/types.hh"
  36 #include "base/logging.hh"
  37 #include "cpu/reg_class.hh"
  38 #include "debug/MiscRegs.hh"
  39 #include "sim/sim_object.hh"
  40
  41 struct PowerISAParams;
  42 class ThreadContext;
  43 class Checkpoint;
  44 class EventManager;
  45
  46 namespace PowerISA
  47 {
  48
  49 class ISA : public BaseISA
  50 {
  51   protected:
  52     RegVal dummy;
  53     RegVal miscRegs[NumMiscRegs];
  54
  55   public:
  56     typedef PowerISAParams Params;
  57
  58     void clear() {}
  59
  60   public:
  61     RegVal
  62     readMiscRegNoEffect(int misc_reg) const
  63     {
  64         assert(misc_reg < NumMiscRegs);
  65         int flatIndex = flattenMiscIndex(misc_reg);
  66         auto val = miscRegs[flatIndex];
  67         DPRINTF(MiscRegs, "Reading misc reg %d (%s) as %#x.\n", misc_reg,
  68                 miscRegName[flatIndex], val);
  69         return val;
  70     }
  71
  72     RegVal
  73     readMiscReg(int misc_reg)
  74     {
  75         return readMiscRegNoEffect(misc_reg);
  76     }
  77
  78     void
  79     setMiscRegNoEffect(int misc_reg, RegVal val)
  80     {
  81         assert(misc_reg < NumMiscRegs);
  82         int flatIndex = flattenMiscIndex(misc_reg);
  83         DPRINTF(MiscRegs, "Setting misc reg %d (%s) to %#x.\n", misc_reg,
  84                 miscRegName[flatIndex], val);
  85         miscRegs[flatIndex] = val;
  86     }
  87
  88     void
  89     setMiscReg(int misc_reg, RegVal val)
  90     {
  91         return setMiscRegNoEffect(misc_reg, val);
  92     }
  93
  94     RegId
  95     flattenRegId(const RegId& regId) const
  96     {
  97         switch (regId.classValue()) {
  98             case IntRegClass:
  99                 return RegId(IntRegClass, flattenIntIndex(regId.index()));
 100             case FloatRegClass:
 101                 return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
 102             case VecRegClass:
 103                 return RegId(VecRegClass, flattenVecIndex(regId.index()));
 104             case VecElemClass:
 105                 return RegId(VecElemClass, flattenVecElemIndex(regId.index()),
 106                              regId.elemIndex());
 107             case VecPredRegClass:
 108                 return RegId(VecPredRegClass,
 109                              flattenVecPredIndex(regId.index()));
 110             case CCRegClass:
 111                 return RegId(CCRegClass, flattenCCIndex(regId.index()));
 112             case MiscRegClass:
 113                 return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
 114         }
 115
 116         return RegId();
 117     }
 118
 119     int
 120     flattenIntIndex(int reg) const
 121     {
 122         return reg;
 123     }
 124
 125     int
 126     flattenFloatIndex(int reg) const
 127     {
 128         return reg;
 129     }
 130
 131     int
 132     flattenVecIndex(int reg) const
 133     {
 134         return reg;
 135     }
 136
 137     int
 138     flattenVecElemIndex(int reg) const
 139     {
 140         return reg;
 141     }
 142
 143     int
 144     flattenVecPredIndex(int reg) const
 145     {
 146         return reg;
 147     }
 148
 149     // dummy
 150     int
 151     flattenCCIndex(int reg) const
 152     {
 153         return reg;
 154     }
 155
 156     int
 157     flattenMiscIndex(int reg) const
 158     {
 159         return reg;
 160     }
 161
 162     const Params &params() const;
 163
 164     ISA(const Params &p);
 165 };
 166
 167 } // namespace PowerISA
 168
 169 #endif // __ARCH_POWER_ISA_HH__