src/arch/power/miscregs.hh

   1 /*
   2  * Copyright (c) 2009 The University of Edinburgh
   3  * Copyright (c) 2021 IBM Corporation
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #ifndef __ARCH_POWER_MISCREGS_HH__
  31 #define __ARCH_POWER_MISCREGS_HH__
  32
  33 #include "base/bitunion.hh"
  34
  35 namespace PowerISA
  36 {
  37
  38 enum MiscRegIndex {
  39     MISCREG_CR,
  40     MISCREG_FPSCR,
  41     MISCREG_XER,
  42     MISCREG_LR,
  43     MISCREG_CTR,
  44     MISCREG_TAR,
  45     MISCREG_MSR,
  46     NUM_MISCREGS
  47 };
  48
  49 const char * const miscRegName[NUM_MISCREGS] = {
  50     "CR",
  51     "FPSCR",
  52     "XER",
  53     "LR",
  54     "CTR",
  55     "TAR",
  56     "MSR"
  57 };
  58
  59 BitUnion32(Cr)
  60     SubBitUnion(cr0, 31, 28)
  61         Bitfield<31> lt;
  62         Bitfield<30> gt;
  63         Bitfield<29> eq;
  64         Bitfield<28> so;
  65     EndSubBitUnion(cr0)
  66     Bitfield<27,24> cr1;
  67 EndBitUnion(Cr)
  68
  69 BitUnion32(Xer)
  70     Bitfield<31> so;
  71     Bitfield<30> ov;
  72     Bitfield<29> ca;
  73     Bitfield<19> ov32;
  74     Bitfield<18> ca32;
  75 EndBitUnion(Xer)
  76
  77 BitUnion32(Fpscr)
  78     Bitfield<31> fx;
  79     Bitfield<30> fex;
  80     Bitfield<29> vx;
  81     Bitfield<28> ox;
  82     Bitfield<27> ux;
  83     Bitfield<26> zx;
  84     Bitfield<25> xx;
  85     Bitfield<24> vxsnan;
  86     Bitfield<23> vxisi;
  87     Bitfield<22> vxidi;
  88     Bitfield<21> vxzdz;
  89     Bitfield<20> vximz;
  90     Bitfield<19> vxvc;
  91     Bitfield<18> fr;
  92     Bitfield<17> fi;
  93     SubBitUnion(fprf, 16, 12)
  94         Bitfield<16> c;
  95         SubBitUnion(fpcc, 15, 12)
  96             Bitfield<15> fl;
  97             Bitfield<14> fg;
  98             Bitfield<13> fe;
  99             Bitfield<12> fu;
 100         EndSubBitUnion(fpcc)
 101     EndSubBitUnion(fprf)
 102     Bitfield<10> vxsqrt;
 103     Bitfield<9> vxcvi;
 104     Bitfield<8> ve;
 105     Bitfield<7> oe;
 106     Bitfield<6> ue;
 107     Bitfield<5> ze;
 108     Bitfield<4> xe;
 109     Bitfield<3> ni;
 110     Bitfield<2,1> rn;
 111 EndBitUnion(Fpscr)
 112
 113 BitUnion64(Msr)
 114     Bitfield<63> sf;
 115     Bitfield<60> hv;
 116     Bitfield<34, 33> ts;
 117     Bitfield<32> tm;
 118     Bitfield<25> vec;
 119     Bitfield<23> vsx;
 120     Bitfield<15> ee;
 121     Bitfield<14> pr;
 122     Bitfield<13> fp;
 123     Bitfield<12> me;
 124     Bitfield<11> fe0;
 125     Bitfield<10, 9> te;
 126     Bitfield<8> fe1;
 127     Bitfield<5> ir;
 128     Bitfield<4> dr;
 129     Bitfield<2> pmm;
 130     Bitfield<1> ri;
 131     Bitfield<0> le;
 132 EndBitUnion(Msr)
 133 } // namespace PowerISA
 134
 135 #endif // __ARCH_POWER_MISCREGS_HH__