ARM: Explicitly keep track of the second destination for double loads/stores.
[gem5.git] / src / arch / power / predecoder.hh
1 /*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * Copyright (c) 2009 The University of Edinburgh
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution;
14 * neither the name of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * Authors: Gabe Black
31 * Stephen Hines
32 * Timothy M. Jones
33 */
34
35 #ifndef __ARCH_ARM_PREDECODER_HH__
36 #define __ARCH_ARM_PREDECODER_HH__
37
38 #include "arch/power/types.hh"
39 #include "base/misc.hh"
40 #include "base/types.hh"
41
42 class ThreadContext;
43
44 namespace PowerISA
45 {
46
47 class Predecoder
48 {
49 protected:
50 ThreadContext * tc;
51
52 // The extended machine instruction being generated
53 ExtMachInst emi;
54
55 public:
56 Predecoder(ThreadContext * _tc)
57 : tc(_tc)
58 {
59 }
60
61 ThreadContext *
62 getTC()
63 {
64 return tc;
65 }
66
67 void
68 setTC(ThreadContext * _tc)
69 {
70 tc = _tc;
71 }
72
73 void
74 process()
75 {
76 }
77
78 void
79 reset()
80 {
81 }
82
83 // Use this to give data to the predecoder. This should be used
84 // when there is control flow.
85 void
86 moreBytes(Addr pc, Addr fetchPC, MachInst inst)
87 {
88 emi = inst;
89 }
90
91 // Use this to give data to the predecoder. This should be used
92 // when instructions are executed in order.
93 void
94 moreBytes(MachInst machInst)
95 {
96 moreBytes(0, 0, machInst);
97 }
98
99 bool
100 needMoreBytes()
101 {
102 return true;
103 }
104
105 bool
106 extMachInstReady()
107 {
108 return true;
109 }
110
111 // This returns a constant reference to the ExtMachInst to avoid a copy
112 const ExtMachInst &
113 getExtMachInst()
114 {
115 return emi;
116 }
117 };
118
119 } // PowerISA namespace
120
121 #endif // __ARCH_POWER_PREDECODER_HH__