2 * Copyright (c) 2009 The University of Edinburgh
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Timothy M. Jones
31 #ifndef __ARCH_POWER_REGISTERS_HH__
32 #define __ARCH_POWER_REGISTERS_HH__
34 #include "arch/power/generated/max_inst_regs.hh"
35 #include "arch/power/miscregs.hh"
39 using PowerISAInst::MaxInstSrcRegs;
40 using PowerISAInst::MaxInstDestRegs;
42 typedef uint8_t RegIndex;
44 typedef uint64_t IntReg;
46 // Floating point register file entry type
47 typedef uint64_t FloatRegBits;
48 typedef double FloatReg;
49 typedef uint64_t MiscReg;
51 // Constants Related to the number of registers
52 const int NumIntArchRegs = 32;
54 // CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR
55 // and zero register, which doesn't actually exist but needs a number
56 const int NumIntSpecialRegs = 9;
57 const int NumFloatArchRegs = 32;
58 const int NumFloatSpecialRegs = 0;
59 const int NumInternalProcRegs = 0;
61 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
62 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
63 const int NumMiscRegs = NUM_MISCREGS;
65 // Semantically meaningful register indices
66 const int ReturnValueReg = 3;
67 const int ArgumentReg0 = 3;
68 const int ArgumentReg1 = 4;
69 const int ArgumentReg2 = 5;
70 const int ArgumentReg3 = 6;
71 const int ArgumentReg4 = 7;
72 const int FramePointerReg = 31;
73 const int StackPointerReg = 1;
75 // There isn't one in Power, but we need to define one somewhere
76 const int ZeroReg = NumIntRegs - 1;
78 const int SyscallNumReg = 0;
79 const int SyscallPseudoReturnReg = 3;
80 const int SyscallSuccessReg = 3;
82 // These help enumerate all the registers for dependence tracking.
83 const int FP_Base_DepTag = NumIntRegs;
84 const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
85 const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs;
94 INTREG_CR = NumIntArchRegs,
104 } // namespace PowerISA
106 #endif // __ARCH_POWER_REGISTERS_HH__