src/arch/power/registers.hh

   1 /*
   2  * Copyright (c) 2009 The University of Edinburgh
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Timothy M. Jones
  29  */
  30
  31 #ifndef __ARCH_POWER_REGISTERS_HH__
  32 #define __ARCH_POWER_REGISTERS_HH__
  33
  34 #include "arch/power/generated/max_inst_regs.hh"
  35 #include "arch/power/miscregs.hh"
  36
  37 namespace PowerISA {
  38
  39 using PowerISAInst::MaxInstSrcRegs;
  40 using PowerISAInst::MaxInstDestRegs;
  41
  42 // Power writes a misc register outside of the isa parser, so it can't
  43 // be detected by it. Manually add it here.
  44 const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1;
  45
  46 typedef uint8_t RegIndex;
  47
  48 typedef uint64_t IntReg;
  49
  50 // Floating point register file entry type
  51 typedef uint64_t FloatRegBits;
  52 typedef double FloatReg;
  53 typedef uint64_t MiscReg;
  54
  55 // dummy typedef since we don't have CC regs
  56 typedef uint8_t CCReg;
  57
  58 // Constants Related to the number of registers
  59 const int NumIntArchRegs = 32;
  60
  61 // CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR
  62 // and zero register, which doesn't actually exist but needs a number
  63 const int NumIntSpecialRegs = 9;
  64 const int NumFloatArchRegs = 32;
  65 const int NumFloatSpecialRegs = 0;
  66 const int NumInternalProcRegs = 0;
  67
  68 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
  69 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
  70 const int NumCCRegs = 0;
  71 const int NumMiscRegs = NUM_MISCREGS;
  72
  73 // Semantically meaningful register indices
  74 const int ReturnValueReg = 3;
  75 const int ArgumentReg0 = 3;
  76 const int ArgumentReg1 = 4;
  77 const int ArgumentReg2 = 5;
  78 const int ArgumentReg3 = 6;
  79 const int ArgumentReg4 = 7;
  80 const int FramePointerReg = 31;
  81 const int StackPointerReg = 1;
  82
  83 // There isn't one in Power, but we need to define one somewhere
  84 const int ZeroReg = NumIntRegs - 1;
  85
  86 const int SyscallNumReg = 0;
  87 const int SyscallPseudoReturnReg = 3;
  88 const int SyscallSuccessReg = 3;
  89
  90 // These help enumerate all the registers for dependence tracking.
  91 const int FP_Reg_Base = NumIntRegs;
  92 const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
  93 const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0
  94 const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
  95
  96 typedef union {
  97     IntReg   intreg;
  98     FloatReg fpreg;
  99     MiscReg  ctrlreg;
 100 } AnyReg;
 101
 102 enum MiscIntRegNums {
 103     INTREG_CR = NumIntArchRegs,
 104     INTREG_XER,
 105     INTREG_LR,
 106     INTREG_CTR,
 107     INTREG_FPSCR,
 108     INTREG_RSV,
 109     INTREG_RSV_LEN,
 110     INTREG_RSV_ADDR
 111 };
 112
 113 } // namespace PowerISA
 114
 115 #endif // __ARCH_POWER_REGISTERS_HH__