2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * Copyright (c) 2009 The University of Edinburgh
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are
10 * met: redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer;
12 * redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution;
15 * neither the name of the copyright holders nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
22 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
23 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
25 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * Authors: Nathan Binkert
41 #include "arch/power/faults.hh"
42 #include "arch/power/pagetable.hh"
43 #include "arch/power/tlb.hh"
44 #include "arch/power/utility.hh"
45 #include "base/inifile.hh"
46 #include "base/str.hh"
47 #include "base/trace.hh"
48 #include "cpu/thread_context.hh"
49 #include "debug/Power.hh"
50 #include "debug/TLB.hh"
51 #include "mem/page_table.hh"
52 #include "params/PowerTLB.hh"
53 #include "sim/full_system.hh"
54 #include "sim/process.hh"
57 using namespace PowerISA
;
59 ///////////////////////////////////////////////////////////////////////
64 #define MODE2MASK(X) (1 << (X))
66 TLB::TLB(const Params
*p
)
67 : BaseTLB(p
), size(p
->size
), nlu(0)
69 table
= new PowerISA::PTE
[size
];
70 memset(table
, 0, sizeof(PowerISA::PTE
[size
]));
80 // look up an entry in the TLB
82 TLB::lookup(Addr vpn
, uint8_t asn
) const
84 // assume not found...
85 PowerISA::PTE
*retval
= NULL
;
86 PageTable::const_iterator i
= lookupTable
.find(vpn
);
87 if (i
!= lookupTable
.end()) {
88 while (i
->first
== vpn
) {
89 int index
= i
->second
;
90 PowerISA::PTE
*pte
= &table
[index
];
91 Addr Mask
= pte
->Mask
;
94 if (((vpn
& InvMask
) == (VPN
& InvMask
))
95 && (pte
->G
|| (asn
== pte
->asid
))) {
97 // We have a VPN + ASID Match
105 DPRINTF(TLB
, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn
, (int)asn
,
106 retval
? "hit" : "miss", retval
? retval
->PFN1
: 0);
111 TLB::getEntry(unsigned Index
) const
113 // Make sure that Index is valid
115 return &table
[Index
];
119 TLB::probeEntry(Addr vpn
,uint8_t asn
) const
121 // assume not found...
122 PowerISA::PTE
*retval
= NULL
;
124 PageTable::const_iterator i
= lookupTable
.find(vpn
);
125 if (i
!= lookupTable
.end()) {
126 while (i
->first
== vpn
) {
127 int index
= i
->second
;
128 PowerISA::PTE
*pte
= &table
[index
];
129 Addr Mask
= pte
->Mask
;
130 Addr InvMask
= ~Mask
;
132 if (((vpn
& InvMask
) == (VPN
& InvMask
))
133 && (pte
->G
|| (asn
== pte
->asid
))) {
135 // We have a VPN + ASID Match
144 DPRINTF(Power
, "VPN: %x, asid: %d, Result of TLBP: %d\n", vpn
, asn
, Ind
);
149 TLB::checkCacheability(RequestPtr
&req
)
151 Addr VAddrUncacheable
= 0xA0000000;
152 if ((req
->getVaddr() & VAddrUncacheable
) == VAddrUncacheable
) {
154 // mark request as uncacheable
155 req
->setFlags(Request::UNCACHEABLE
);
161 TLB::insertAt(PowerISA::PTE
&pte
, unsigned Index
, int _smallPages
)
163 smallPages
=_smallPages
;
165 warn("Attempted to write at index (%d) beyond TLB size (%d)",
170 if (table
[Index
].V0
== true || table
[Index
].V1
== true) {
172 // Previous entry is valid
173 PageTable::iterator i
= lookupTable
.find(table
[Index
].VPN
);
174 lookupTable
.erase(i
);
178 // Update fast lookup table
179 lookupTable
.insert(make_pair(table
[Index
].VPN
, Index
));
183 // insert a new TLB entry
185 TLB::insert(Addr addr
, PowerISA::PTE
&pte
)
187 fatal("TLB Insert not yet implemented\n");
193 DPRINTF(TLB
, "flushAll\n");
194 memset(table
, 0, sizeof(PowerISA::PTE
[size
]));
200 TLB::serialize(ostream
&os
)
202 SERIALIZE_SCALAR(size
);
203 SERIALIZE_SCALAR(nlu
);
205 for (int i
= 0; i
< size
; i
++) {
206 nameOut(os
, csprintf("%s.PTE%d", name(), i
));
207 table
[i
].serialize(os
);
212 TLB::unserialize(Checkpoint
*cp
, const string
§ion
)
214 UNSERIALIZE_SCALAR(size
);
215 UNSERIALIZE_SCALAR(nlu
);
217 for (int i
= 0; i
< size
; i
++) {
218 table
[i
].unserialize(cp
, csprintf("%s.PTE%d", section
, i
));
219 if (table
[i
].V0
|| table
[i
].V1
) {
220 lookupTable
.insert(make_pair(table
[i
].VPN
, i
));
229 .name(name() + ".read_hits")
230 .desc("DTB read hits")
234 .name(name() + ".read_misses")
235 .desc("DTB read misses")
240 .name(name() + ".read_accesses")
241 .desc("DTB read accesses")
245 .name(name() + ".write_hits")
246 .desc("DTB write hits")
250 .name(name() + ".write_misses")
251 .desc("DTB write misses")
256 .name(name() + ".write_accesses")
257 .desc("DTB write accesses")
261 .name(name() + ".hits")
266 .name(name() + ".misses")
271 .name(name() + ".accesses")
272 .desc("DTB accesses")
275 hits
= read_hits
+ write_hits
;
276 misses
= read_misses
+ write_misses
;
277 accesses
= read_accesses
+ write_accesses
;
281 TLB::translateInst(RequestPtr req
, ThreadContext
*tc
)
283 // Instruction accesses must be word-aligned
284 if (req
->getVaddr() & 0x3) {
285 DPRINTF(TLB
, "Alignment Fault on %#x, size = %d\n", req
->getVaddr(),
287 return new AlignmentFault();
290 Process
* p
= tc
->getProcessPtr();
292 Fault fault
= p
->pTable
->translate(req
);
293 if (fault
!= NoFault
)
300 TLB::translateData(RequestPtr req
, ThreadContext
*tc
, bool write
)
302 Process
* p
= tc
->getProcessPtr();
304 Fault fault
= p
->pTable
->translate(req
);
305 if (fault
!= NoFault
)
312 TLB::translateAtomic(RequestPtr req
, ThreadContext
*tc
, Mode mode
)
315 fatal("translate atomic not yet implemented in full system mode.\n");
318 return translateInst(req
, tc
);
320 return translateData(req
, tc
, mode
== Write
);
325 TLB::translateTiming(RequestPtr req
, ThreadContext
*tc
,
326 Translation
*translation
, Mode mode
)
329 translation
->finish(translateAtomic(req
, tc
, mode
), req
, tc
, mode
);
333 TLB::index(bool advance
)
335 PowerISA::PTE
*pte
= &table
[nlu
];
344 PowerTLBParams::create()
346 return new PowerISA::TLB(this);