src/arch/power/tlb.cc

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * Copyright (c) 2007 MIPS Technologies, Inc.
   4  * Copyright (c) 2007-2008 The Florida State University
   5  * Copyright (c) 2009 The University of Edinburgh
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions are
  10  * met: redistributions of source code must retain the above copyright
  11  * notice, this list of conditions and the following disclaimer;
  12  * redistributions in binary form must reproduce the above copyright
  13  * notice, this list of conditions and the following disclaimer in the
  14  * documentation and/or other materials provided with the distribution;
  15  * neither the name of the copyright holders nor the names of its
  16  * contributors may be used to endorse or promote products derived from
  17  * this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  20  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  21  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  22  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  23  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  24  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  25  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  29  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include "arch/power/tlb.hh"
  33
  34 #include <string>
  35 #include <vector>
  36
  37 #include "arch/power/faults.hh"
  38 #include "arch/power/pagetable.hh"
  39 #include "arch/power/utility.hh"
  40 #include "base/inifile.hh"
  41 #include "base/str.hh"
  42 #include "base/trace.hh"
  43 #include "cpu/thread_context.hh"
  44 #include "debug/Power.hh"
  45 #include "debug/TLB.hh"
  46 #include "mem/page_table.hh"
  47 #include "params/PowerTLB.hh"
  48 #include "sim/full_system.hh"
  49 #include "sim/process.hh"
  50
  51 using namespace PowerISA;
  52
  53 ///////////////////////////////////////////////////////////////////////
  54 //
  55 //  POWER TLB
  56 //
  57
  58 #define MODE2MASK(X) (1 << (X))
  59
  60 TLB::TLB(const Params &p) : BaseTLB(p), size(p.size), nlu(0)
  61 {
  62     table = new PowerISA::PTE[size];
  63     memset(table, 0, sizeof(PowerISA::PTE[size]));
  64     smallPages = 0;
  65 }
  66
  67 TLB::~TLB()
  68 {
  69     if (table)
  70         delete [] table;
  71 }
  72
  73 // look up an entry in the TLB
  74 PowerISA::PTE *
  75 TLB::lookup(Addr vpn, uint8_t asn) const
  76 {
  77     // assume not found...
  78     PowerISA::PTE *retval = NULL;
  79     PageTable::const_iterator i = lookupTable.find(vpn);
  80     if (i != lookupTable.end()) {
  81         while (i->first == vpn) {
  82             int index = i->second;
  83             PowerISA::PTE *pte = &table[index];
  84             Addr Mask = pte->Mask;
  85             Addr InvMask = ~Mask;
  86             Addr VPN  = pte->VPN;
  87             if (((vpn & InvMask) == (VPN & InvMask))
  88                && (pte->G  || (asn == pte->asid))) {
  89
  90                 // We have a VPN + ASID Match
  91                 retval = pte;
  92                 break;
  93             }
  94             ++i;
  95         }
  96     }
  97
  98     DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
  99             retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
 100     return retval;
 101 }
 102
 103 PowerISA::PTE*
 104 TLB::getEntry(unsigned Index) const
 105 {
 106     // Make sure that Index is valid
 107     assert(Index<size);
 108     return &table[Index];
 109 }
 110
 111 int
 112 TLB::probeEntry(Addr vpn,uint8_t asn) const
 113 {
 114     // assume not found...
 115     int Ind = -1;
 116     PageTable::const_iterator i = lookupTable.find(vpn);
 117     if (i != lookupTable.end()) {
 118         while (i->first == vpn) {
 119             int index = i->second;
 120             PowerISA::PTE *pte = &table[index];
 121             Addr Mask = pte->Mask;
 122             Addr InvMask = ~Mask;
 123             Addr VPN  = pte->VPN;
 124             if (((vpn & InvMask) == (VPN & InvMask))
 125                 && (pte->G  || (asn == pte->asid))) {
 126
 127                 // We have a VPN + ASID Match
 128                 Ind = index;
 129                 break;
 130             }
 131             ++i;
 132         }
 133     }
 134
 135     DPRINTF(Power, "VPN: %x, asid: %d, Result of TLBP: %d\n", vpn, asn, Ind);
 136     return Ind;
 137 }
 138
 139 inline Fault
 140 TLB::checkCacheability(const RequestPtr &req)
 141 {
 142     Addr VAddrUncacheable = 0xA0000000;
 143     if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
 144
 145         // mark request as uncacheable
 146         req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
 147     }
 148     return NoFault;
 149 }
 150
 151 void
 152 TLB::insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages)
 153 {
 154     smallPages=_smallPages;
 155     if (Index > size){
 156         warn("Attempted to write at index (%d) beyond TLB size (%d)",
 157              Index, size);
 158     } else {
 159
 160         // Update TLB
 161         if (table[Index].V0 || table[Index].V1) {
 162
 163             // Previous entry is valid
 164             PageTable::iterator i = lookupTable.find(table[Index].VPN);
 165             lookupTable.erase(i);
 166         }
 167         table[Index]=pte;
 168
 169         // Update fast lookup table
 170         lookupTable.insert(std::make_pair(table[Index].VPN, Index));
 171     }
 172 }
 173
 174 // insert a new TLB entry
 175 void
 176 TLB::insert(Addr addr, PowerISA::PTE &pte)
 177 {
 178     fatal("TLB Insert not yet implemented\n");
 179 }
 180
 181 void
 182 TLB::flushAll()
 183 {
 184     DPRINTF(TLB, "flushAll\n");
 185     memset(table, 0, sizeof(PowerISA::PTE[size]));
 186     lookupTable.clear();
 187     nlu = 0;
 188 }
 189
 190 void
 191 TLB::serialize(CheckpointOut &cp) const
 192 {
 193     SERIALIZE_SCALAR(size);
 194     SERIALIZE_SCALAR(nlu);
 195
 196     for (int i = 0; i < size; i++) {
 197         ScopedCheckpointSection sec(cp, csprintf("PTE%d", i));
 198         table[i].serialize(cp);
 199     }
 200 }
 201
 202 void
 203 TLB::unserialize(CheckpointIn &cp)
 204 {
 205     UNSERIALIZE_SCALAR(size);
 206     UNSERIALIZE_SCALAR(nlu);
 207
 208     for (int i = 0; i < size; i++) {
 209         ScopedCheckpointSection sec(cp, csprintf("PTE%d", i));
 210         if (table[i].V0 || table[i].V1) {
 211             lookupTable.insert(std::make_pair(table[i].VPN, i));
 212         }
 213     }
 214 }
 215
 216 Fault
 217 TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
 218 {
 219     // Instruction accesses must be word-aligned
 220     if (req->getVaddr() & 0x3) {
 221         DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(),
 222                 req->getSize());
 223         return std::make_shared<AlignmentFault>();
 224     }
 225
 226     return tc->getProcessPtr()->pTable->translate(req);
 227 }
 228
 229 Fault
 230 TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
 231 {
 232     return tc->getProcessPtr()->pTable->translate(req);
 233 }
 234
 235 Fault
 236 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
 237 {
 238     panic_if(FullSystem,
 239             "translateAtomic not yet implemented for full system.");
 240
 241     if (mode == Execute)
 242         return translateInst(req, tc);
 243     else
 244         return translateData(req, tc, mode == Write);
 245 }
 246
 247 Fault
 248 TLB::translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
 249 {
 250     panic_if(FullSystem,
 251             "translateFunctional not implemented for full system.");
 252     return tc->getProcessPtr()->pTable->translate(req);
 253 }
 254
 255 void
 256 TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
 257                      Translation *translation, Mode mode)
 258 {
 259     assert(translation);
 260     translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
 261 }
 262
 263 Fault
 264 TLB::finalizePhysical(const RequestPtr &req,
 265                       ThreadContext *tc, Mode mode) const
 266 {
 267     return NoFault;
 268 }
 269
 270 PowerISA::PTE &
 271 TLB::index(bool advance)
 272 {
 273     PowerISA::PTE *pte = &table[nlu];
 274
 275     if (advance)
 276         nextnlu();
 277
 278     return *pte;
 279 }