2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * Copyright (c) 2009 The University of Edinburgh
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are
10 * met: redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer;
12 * redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution;
15 * neither the name of the copyright holders nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
22 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
23 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
25 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * Authors: Nathan Binkert
37 #ifndef __ARCH_POWER_TLB_HH__
38 #define __ARCH_POWER_TLB_HH__
42 #include "arch/power/isa_traits.hh"
43 #include "arch/power/pagetable.hh"
44 #include "arch/power/utility.hh"
45 #include "arch/power/vtophys.hh"
46 #include "base/statistics.hh"
47 #include "mem/request.hh"
48 #include "params/PowerTLB.hh"
49 #include "sim/fault_fwd.hh"
56 // This is copied from the ARM ISA and has not been checked against the
66 TlbEntry(Addr asn, Addr vaddr, Addr paddr)
72 updateVaddr(Addr new_vaddr)
74 panic("unimplemented");
84 serialize(std::ostream &os)
86 SERIALIZE_SCALAR(_pageStart);
90 unserialize(Checkpoint *cp, const std::string §ion)
92 UNSERIALIZE_SCALAR(_pageStart);
96 class TLB : public BaseTLB
99 typedef std::multimap<Addr, int> PageTable;
100 PageTable lookupTable; // Quick lookup into page table
102 PowerISA::PTE *table; // the Page Table
103 int size; // TLB Size
104 int nlu; // not last used entry (for replacement)
114 PowerISA::PTE *lookup(Addr vpn, uint8_t asn) const;
116 mutable Stats::Scalar read_hits;
117 mutable Stats::Scalar read_misses;
118 mutable Stats::Scalar read_acv;
119 mutable Stats::Scalar read_accesses;
120 mutable Stats::Scalar write_hits;
121 mutable Stats::Scalar write_misses;
122 mutable Stats::Scalar write_acv;
123 mutable Stats::Scalar write_accesses;
125 Stats::Formula misses;
126 Stats::Formula accesses;
129 typedef PowerTLBParams Params;
130 TLB(const Params *p);
133 int probeEntry(Addr vpn,uint8_t) const;
134 PowerISA::PTE *getEntry(unsigned) const;
144 PowerISA::PTE &index(bool advance = true);
145 void insert(Addr vaddr, PowerISA::PTE &pte);
146 void insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages);
150 demapPage(Addr vaddr, uint64_t asn)
152 panic("demapPage unimplemented.\n");
155 // static helper functions... really
156 static bool validVirtualAddress(Addr vaddr);
157 static Fault checkCacheability(RequestPtr &req);
158 Fault translateInst(RequestPtr req, ThreadContext *tc);
159 Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
160 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
161 void translateTiming(RequestPtr req, ThreadContext *tc,
162 Translation *translation, Mode mode);
163 /** Stub function for CheckerCPU compilation support. Power ISA not
164 * supported by Checker at the moment
166 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
169 void serialize(std::ostream &os);
170 void unserialize(Checkpoint *cp, const std::string §ion);
174 } // namespace PowerISA
176 #endif // __ARCH_POWER_TLB_HH__