src/arch/power/types.hh

   1 /*
   2  * Copyright (c) 2009 The University of Edinburgh
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __ARCH_POWER_TYPES_HH__
  30 #define __ARCH_POWER_TYPES_HH__
  31
  32 #include "arch/generic/types.hh"
  33 #include "base/bitunion.hh"
  34 #include "base/types.hh"
  35
  36 namespace PowerISA
  37 {
  38
  39 typedef uint32_t MachInst;
  40
  41 BitUnion32(ExtMachInst)
  42
  43     // Registers
  44     Bitfield<25, 21> rs;
  45     Bitfield<20, 16> ra;
  46
  47     // Shifts and masks
  48     Bitfield<15, 11> sh;
  49     Bitfield<1>      shn;
  50     Bitfield<10,  6> mb;
  51     Bitfield<5>      mbn;
  52     Bitfield< 5,  1> me;
  53     Bitfield<5>      men;
  54
  55     // Immediate fields
  56     Bitfield<15,  0> si;
  57     Bitfield<15,  0> ui;
  58     Bitfield<15,  0> d;
  59     Bitfield<15,  2> ds;
  60     Bitfield<15,  6> d0;
  61     Bitfield<20, 16> d1;
  62     Bitfield< 1,  0> d2;
  63
  64     // Compare fields
  65     Bitfield<21>     l;
  66
  67     // Special purpose register identifier
  68     Bitfield<20, 11> spr;
  69     Bitfield<25,  2> li;
  70     Bitfield<1>      aa;
  71     Bitfield<25, 23> bf;
  72     Bitfield<15,  2> bd;
  73     Bitfield<25, 21> bo;
  74     Bitfield<20, 16> bi;
  75     Bitfield<20, 18> bfa;
  76
  77     // Record bits
  78     Bitfield<0>      rc31;
  79     Bitfield<10>     oe;
  80
  81     // Condition register fields
  82     Bitfield<25, 21> bt;
  83     Bitfield<20, 16> ba;
  84     Bitfield<15, 11> bb;
  85
  86     // FXM field for mtcrf instruction
  87     Bitfield<19, 12> fxm;
  88 EndBitUnion(ExtMachInst)
  89
  90 typedef GenericISA::SimplePCState<MachInst> PCState;
  91
  92 // typedef uint64_t LargestRead;
  93 // // Need to use 64 bits to make sure that read requests get handled properly
  94
  95 // typedef int RegContextParam;
  96 // typedef int RegContextVal;
  97
  98 } // PowerISA namespace
  99
 100 namespace std {
 101
 102 template<>
 103 struct hash<PowerISA::ExtMachInst> : public hash<uint32_t> {
 104     size_t operator()(const PowerISA::ExtMachInst &emi) const {
 105         return hash<uint32_t>::operator()((uint32_t)emi);
 106     };
 107 };
 108
 109 }
 110
 111 #endif // __ARCH_POWER_TYPES_HH__