misc: Merge branch 'release-staging-v20.0.0.0' into develop
[gem5.git] / src / arch / riscv / bare_metal / fs_workload.hh
1 /*
2 * Copyright (c) 2018 TU Dresden
3 * All rights reserved
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #ifndef __ARCH_RISCV_BARE_METAL_SYSTEM_HH__
30 #define __ARCH_RISCV_BARE_METAL_SYSTEM_HH__
31
32 #include "arch/riscv/fs_workload.hh"
33 #include "params/RiscvBareMetal.hh"
34
35 namespace RiscvISA
36 {
37
38 class BareMetal : public RiscvISA::FsWorkload
39 {
40 protected:
41 Loader::ObjectFile *bootloader;
42 Loader::SymbolTable *bootloaderSymtab;
43
44 public:
45 typedef RiscvBareMetalParams Params;
46 BareMetal(Params *p);
47 ~BareMetal();
48
49 void initState() override;
50
51 Loader::Arch getArch() const override { return bootloader->getArch(); }
52 const Loader::SymbolTable *
53 symtab(ThreadContext *tc) override
54 {
55 return bootloaderSymtab;
56 }
57 bool
58 insertSymbol(const Loader::Symbol &symbol) override
59 {
60 return bootloaderSymtab->insert(symbol);
61 }
62 };
63
64 } // namespace RiscvISA
65
66 #endif // __ARCH_RISCV_BARE_METAL_FS_WORKLOAD_HH__