src/arch/riscv/decoder.cc

   1 /*
   2  * Copyright (c) 2012 Google
   3  * Copyright (c) The University of Virginia
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #include "arch/riscv/decoder.hh"
  31 #include "arch/riscv/types.hh"
  32 #include "debug/Decode.hh"
  33
  34 namespace RiscvISA
  35 {
  36
  37 static const MachInst LowerBitMask = (1 << sizeof(MachInst) * 4) - 1;
  38 static const MachInst UpperBitMask = LowerBitMask << sizeof(MachInst) * 4;
  39
  40 void Decoder::reset()
  41 {
  42     aligned = true;
  43     mid = false;
  44     more = true;
  45     emi = 0;
  46     instDone = false;
  47 }
  48
  49 void
  50 Decoder::moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
  51 {
  52     inst = letoh(inst);
  53     DPRINTF(Decode, "Requesting bytes 0x%08x from address %#x\n", inst,
  54             fetchPC);
  55
  56     bool aligned = pc.pc() % sizeof(MachInst) == 0;
  57     if (aligned) {
  58         emi = inst;
  59         if (compressed(emi))
  60             emi &= LowerBitMask;
  61         more = !compressed(emi);
  62         instDone = true;
  63     } else {
  64         if (mid) {
  65             assert((emi & UpperBitMask) == 0);
  66             emi |= (inst & LowerBitMask) << sizeof(MachInst)*4;
  67             mid = false;
  68             more = false;
  69             instDone = true;
  70         } else {
  71             emi = (inst & UpperBitMask) >> sizeof(MachInst)*4;
  72             mid = !compressed(emi);
  73             more = true;
  74             instDone = compressed(emi);
  75         }
  76     }
  77 }
  78
  79 StaticInstPtr
  80 Decoder::decode(ExtMachInst mach_inst, Addr addr)
  81 {
  82     DPRINTF(Decode, "Decoding instruction 0x%08x at address %#x\n",
  83             mach_inst, addr);
  84     if (instMap.find(mach_inst) != instMap.end())
  85         return instMap[mach_inst];
  86     else {
  87         StaticInstPtr si = decodeInst(mach_inst);
  88         instMap[mach_inst] = si;
  89         return si;
  90     }
  91 }
  92
  93 StaticInstPtr
  94 Decoder::decode(RiscvISA::PCState &nextPC)
  95 {
  96     if (!instDone)
  97         return nullptr;
  98     instDone = false;
  99
 100     if (compressed(emi)) {
 101         nextPC.npc(nextPC.instAddr() + sizeof(MachInst) / 2);
 102     } else {
 103         nextPC.npc(nextPC.instAddr() + sizeof(MachInst));
 104     }
 105
 106     return decode(emi, nextPC.instAddr());
 107 }
 108
 109 }