src/arch/riscv/insts/amo.cc

   1 /*
   2  * Copyright (c) 2015 RISC-V Foundation
   3  * Copyright (c) 2017 The University of Virginia
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #include "arch/riscv/insts/amo.hh"
  31
  32 #include <sstream>
  33 #include <string>
  34
  35 #include "arch/riscv/insts/bitfields.hh"
  36 #include "arch/riscv/utility.hh"
  37 #include "cpu/exec_context.hh"
  38 #include "cpu/static_inst.hh"
  39
  40 using namespace std;
  41
  42 namespace RiscvISA
  43 {
  44
  45 // memfence micro instruction
  46 string
  47 MemFenceMicro::generateDisassembly(
  48         Addr pc, const Loader::SymbolTable *symtab) const
  49 {
  50     stringstream ss;
  51     ss << csprintf("0x%08x", machInst) << ' ' << mnemonic;
  52     return ss.str();
  53 }
  54
  55 Fault MemFenceMicro::execute(ExecContext *xc,
  56     Trace::InstRecord *traceData) const
  57 {
  58     return NoFault;
  59 }
  60
  61 // load-reserved
  62 string
  63 LoadReserved::generateDisassembly(
  64         Addr pc, const Loader::SymbolTable *symtab) const
  65 {
  66     stringstream ss;
  67     ss << mnemonic;
  68     if (AQ || RL)
  69         ss << '_';
  70     if (AQ)
  71         ss << "aq";
  72     if (RL)
  73         ss << "rl";
  74     ss << ' ' << registerName(RegId(IntRegClass, RD)) << ", ("
  75             << registerName(RegId(IntRegClass, RS1)) << ')';
  76     return ss.str();
  77 }
  78
  79 string
  80 LoadReservedMicro::generateDisassembly(
  81         Addr pc, const Loader::SymbolTable *symtab) const
  82 {
  83     stringstream ss;
  84     ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", ("
  85             << registerName(srcRegIdx(0)) << ')';
  86     return ss.str();
  87 }
  88
  89 // store-conditional
  90 string
  91 StoreCond::generateDisassembly(
  92         Addr pc, const Loader::SymbolTable *symtab) const
  93 {
  94     stringstream ss;
  95     ss << mnemonic;
  96     if (AQ || RL)
  97         ss << '_';
  98     if (AQ)
  99         ss << "aq";
 100     if (RL)
 101         ss << "rl";
 102     ss << ' ' << registerName(RegId(IntRegClass, RD)) << ", "
 103             << registerName(RegId(IntRegClass, RS2)) << ", ("
 104             << registerName(RegId(IntRegClass, RS1)) << ')';
 105     return ss.str();
 106 }
 107
 108 string
 109 StoreCondMicro::generateDisassembly(
 110         Addr pc, const Loader::SymbolTable *symtab) const
 111 {
 112     stringstream ss;
 113     ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", "
 114             << registerName(srcRegIdx(1)) << ", ("
 115             << registerName(srcRegIdx(0)) << ')';
 116     return ss.str();
 117 }
 118
 119 // AMOs
 120 string
 121 AtomicMemOp::generateDisassembly(
 122         Addr pc, const Loader::SymbolTable *symtab) const
 123 {
 124     stringstream ss;
 125     ss << mnemonic;
 126     if (AQ || RL)
 127         ss << '_';
 128     if (AQ)
 129         ss << "aq";
 130     if (RL)
 131         ss << "rl";
 132     ss << ' ' << registerName(RegId(IntRegClass, RD)) << ", "
 133             << registerName(RegId(IntRegClass, RS2)) << ", ("
 134             << registerName(RegId(IntRegClass, RS1)) << ')';
 135     return ss.str();
 136 }
 137
 138 string
 139 AtomicMemOpMicro::generateDisassembly(
 140         Addr pc, const Loader::SymbolTable *symtab) const
 141 {
 142     stringstream ss;
 143     ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", "
 144             << registerName(srcRegIdx(1)) << ", ("
 145             << registerName(srcRegIdx(0)) << ')';
 146     return ss.str();
 147 }
 148
 149 }