src/arch/riscv/insts/amo.cc

   1 /*
   2  * Copyright (c) 2015 RISC-V Foundation
   3  * Copyright (c) 2017 The University of Virginia
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #include "arch/riscv/insts/amo.hh"
  31
  32 #include <sstream>
  33 #include <string>
  34
  35 #include "arch/riscv/insts/bitfields.hh"
  36 #include "arch/riscv/utility.hh"
  37 #include "cpu/exec_context.hh"
  38 #include "cpu/static_inst.hh"
  39
  40 namespace RiscvISA
  41 {
  42
  43 // memfence micro instruction
  44 std::string
  45 MemFenceMicro::generateDisassembly(
  46         Addr pc, const Loader::SymbolTable *symtab) const
  47 {
  48     std::stringstream ss;
  49     ss << csprintf("0x%08x", machInst) << ' ' << mnemonic;
  50     return ss.str();
  51 }
  52
  53 Fault MemFenceMicro::execute(ExecContext *xc,
  54     Trace::InstRecord *traceData) const
  55 {
  56     return NoFault;
  57 }
  58
  59 // load-reserved
  60 std::string
  61 LoadReserved::generateDisassembly(
  62         Addr pc, const Loader::SymbolTable *symtab) const
  63 {
  64     std::stringstream ss;
  65     ss << mnemonic;
  66     if (AQ || RL)
  67         ss << '_';
  68     if (AQ)
  69         ss << "aq";
  70     if (RL)
  71         ss << "rl";
  72     ss << ' ' << registerName(RegId(IntRegClass, RD)) << ", ("
  73             << registerName(RegId(IntRegClass, RS1)) << ')';
  74     return ss.str();
  75 }
  76
  77 std::string
  78 LoadReservedMicro::generateDisassembly(
  79         Addr pc, const Loader::SymbolTable *symtab) const
  80 {
  81     std::stringstream ss;
  82     ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", ("
  83             << registerName(srcRegIdx(0)) << ')';
  84     return ss.str();
  85 }
  86
  87 // store-conditional
  88 std::string
  89 StoreCond::generateDisassembly(
  90         Addr pc, const Loader::SymbolTable *symtab) const
  91 {
  92     std::stringstream ss;
  93     ss << mnemonic;
  94     if (AQ || RL)
  95         ss << '_';
  96     if (AQ)
  97         ss << "aq";
  98     if (RL)
  99         ss << "rl";
 100     ss << ' ' << registerName(RegId(IntRegClass, RD)) << ", "
 101             << registerName(RegId(IntRegClass, RS2)) << ", ("
 102             << registerName(RegId(IntRegClass, RS1)) << ')';
 103     return ss.str();
 104 }
 105
 106 std::string
 107 StoreCondMicro::generateDisassembly(
 108         Addr pc, const Loader::SymbolTable *symtab) const
 109 {
 110     std::stringstream ss;
 111     ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", "
 112             << registerName(srcRegIdx(1)) << ", ("
 113             << registerName(srcRegIdx(0)) << ')';
 114     return ss.str();
 115 }
 116
 117 // AMOs
 118 std::string
 119 AtomicMemOp::generateDisassembly(
 120         Addr pc, const Loader::SymbolTable *symtab) const
 121 {
 122     std::stringstream ss;
 123     ss << mnemonic;
 124     if (AQ || RL)
 125         ss << '_';
 126     if (AQ)
 127         ss << "aq";
 128     if (RL)
 129         ss << "rl";
 130     ss << ' ' << registerName(RegId(IntRegClass, RD)) << ", "
 131             << registerName(RegId(IntRegClass, RS2)) << ", ("
 132             << registerName(RegId(IntRegClass, RS1)) << ')';
 133     return ss.str();
 134 }
 135
 136 std::string
 137 AtomicMemOpMicro::generateDisassembly(
 138         Addr pc, const Loader::SymbolTable *symtab) const
 139 {
 140     std::stringstream ss;
 141     ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", "
 142             << registerName(srcRegIdx(1)) << ", ("
 143             << registerName(srcRegIdx(0)) << ')';
 144     return ss.str();
 145 }
 146
 147 }