src/arch/riscv/insts/amo.cc

   1 /*
   2  * Copyright (c) 2015 RISC-V Foundation
   3  * Copyright (c) 2017 The University of Virginia
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * Authors: Alec Roelke
  30  */
  31
  32 #include "arch/riscv/insts/amo.hh"
  33
  34 #include <sstream>
  35 #include <string>
  36
  37 #include "arch/riscv/utility.hh"
  38 #include "cpu/exec_context.hh"
  39 #include "cpu/static_inst.hh"
  40
  41 using namespace std;
  42
  43 namespace RiscvISA
  44 {
  45
  46 // memfence micro instruction
  47 string MemFenceMicro::generateDisassembly(Addr pc,
  48     const SymbolTable *symtab) const
  49 {
  50     stringstream ss;
  51     ss << csprintf("0x%08x", machInst) << ' ' << mnemonic;
  52     return ss.str();
  53 }
  54
  55 Fault MemFenceMicro::execute(ExecContext *xc,
  56     Trace::InstRecord *traceData) const
  57 {
  58     return NoFault;
  59 }
  60
  61 // load-reserved
  62 string LoadReserved::generateDisassembly(Addr pc,
  63     const SymbolTable *symtab) const
  64 {
  65     stringstream ss;
  66     ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ("
  67             << registerName(_srcRegIdx[0]) << ')';
  68     return ss.str();
  69 }
  70
  71 string LoadReservedMicro::generateDisassembly(Addr pc,
  72     const SymbolTable *symtab) const
  73 {
  74     stringstream ss;
  75     ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ("
  76             << registerName(_srcRegIdx[0]) << ')';
  77     return ss.str();
  78 }
  79
  80 // store-conditional
  81 string StoreCond::generateDisassembly(Addr pc,
  82     const SymbolTable *symtab) const
  83 {
  84     stringstream ss;
  85     ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
  86             << registerName(_srcRegIdx[1]) << ", ("
  87             << registerName(_srcRegIdx[0]) << ')';
  88     return ss.str();
  89 }
  90
  91 string StoreCondMicro::generateDisassembly(Addr pc,
  92     const SymbolTable *symtab) const
  93 {
  94     stringstream ss;
  95     ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
  96             << registerName(_srcRegIdx[1]) << ", ("
  97             << registerName(_srcRegIdx[0]) << ')';
  98     return ss.str();
  99 }
 100
 101 // AMOs
 102 string AtomicMemOp::generateDisassembly(Addr pc,
 103     const SymbolTable *symtab) const
 104 {
 105     stringstream ss;
 106     ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
 107             << registerName(_srcRegIdx[1]) << ", ("
 108             << registerName(_srcRegIdx[0]) << ')';
 109     return ss.str();
 110 }
 111
 112 string AtomicMemOpMicro::generateDisassembly(Addr pc,
 113     const SymbolTable *symtab) const
 114 {
 115     stringstream ss;
 116     ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
 117             << registerName(_srcRegIdx[1]) << ", ("
 118             << registerName(_srcRegIdx[0]) << ')';
 119     return ss.str();
 120 }
 121
 122 }