src/arch/riscv/insts/mem.cc

   1 /*
   2  * Copyright (c) 2015 RISC-V Foundation
   3  * Copyright (c) 2017 The University of Virginia
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #include "arch/riscv/insts/mem.hh"
  31
  32 #include <sstream>
  33 #include <string>
  34
  35 #include "arch/riscv/insts/bitfields.hh"
  36 #include "arch/riscv/insts/static_inst.hh"
  37 #include "arch/riscv/utility.hh"
  38 #include "cpu/static_inst.hh"
  39
  40 using namespace std;
  41
  42 namespace RiscvISA
  43 {
  44
  45 string
  46 Load::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
  47 {
  48     stringstream ss;
  49     ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<
  50         offset << '(' << registerName(srcRegIdx(0)) << ')';
  51     return ss.str();
  52 }
  53
  54 string
  55 Store::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
  56 {
  57     stringstream ss;
  58     ss << mnemonic << ' ' << registerName(srcRegIdx(1)) << ", " <<
  59         offset << '(' << registerName(srcRegIdx(0)) << ')';
  60     return ss.str();
  61 }
  62
  63 }