src/arch/riscv/insts/standard.cc

   1 /*
   2  * Copyright (c) 2015 RISC-V Foundation
   3  * Copyright (c) 2017 The University of Virginia
   4  * Copyright (c) 2020 Barkhausen Institut
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are
   9  * met: redistributions of source code must retain the above copyright
  10  * notice, this list of conditions and the following disclaimer;
  11  * redistributions in binary form must reproduce the above copyright
  12  * notice, this list of conditions and the following disclaimer in the
  13  * documentation and/or other materials provided with the distribution;
  14  * neither the name of the copyright holders nor the names of its
  15  * contributors may be used to endorse or promote products derived from
  16  * this software without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  24  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  26  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  28  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 #include "arch/riscv/insts/standard.hh"
  32
  33 #include <sstream>
  34 #include <string>
  35
  36 #include "arch/riscv/insts/static_inst.hh"
  37 #include "arch/riscv/utility.hh"
  38 #include "cpu/static_inst.hh"
  39
  40 using namespace std;
  41
  42 namespace RiscvISA
  43 {
  44
  45 string
  46 RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
  47 {
  48     stringstream ss;
  49     ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
  50         registerName(_srcRegIdx[0]) << ", " <<
  51         registerName(_srcRegIdx[1]);
  52     return ss.str();
  53 }
  54
  55 string
  56 CSROp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
  57 {
  58     stringstream ss;
  59     ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ";
  60     if (_numSrcRegs > 0)
  61         ss << registerName(_srcRegIdx[0]) << ", ";
  62     auto data = CSRData.find(csr);
  63     if (data != CSRData.end())
  64         ss << data->second.name;
  65     else
  66         ss << "?? (" << hex << "0x" << csr << ")";
  67     return ss.str();
  68 }
  69
  70 string
  71 SystemOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
  72 {
  73     if (strcmp(mnemonic, "fence_vma") == 0) {
  74         stringstream ss;
  75         ss << mnemonic << ' ' << registerName(_srcRegIdx[0]) << ", " <<
  76             registerName(_srcRegIdx[1]);
  77         return ss.str();
  78     }
  79
  80     return mnemonic;
  81 }
  82
  83 }