src/arch/riscv/insts/standard.cc

   1 /*
   2  * Copyright (c) 2015 RISC-V Foundation
   3  * Copyright (c) 2017 The University of Virginia
   4  * Copyright (c) 2020 Barkhausen Institut
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are
   9  * met: redistributions of source code must retain the above copyright
  10  * notice, this list of conditions and the following disclaimer;
  11  * redistributions in binary form must reproduce the above copyright
  12  * notice, this list of conditions and the following disclaimer in the
  13  * documentation and/or other materials provided with the distribution;
  14  * neither the name of the copyright holders nor the names of its
  15  * contributors may be used to endorse or promote products derived from
  16  * this software without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  24  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  26  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  28  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 #include "arch/riscv/insts/standard.hh"
  32
  33 #include <sstream>
  34 #include <string>
  35
  36 #include "arch/riscv/insts/static_inst.hh"
  37 #include "arch/riscv/utility.hh"
  38 #include "cpu/static_inst.hh"
  39
  40 namespace RiscvISA
  41 {
  42
  43 std::string
  44 RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
  45 {
  46     std::stringstream ss;
  47     ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<
  48         registerName(srcRegIdx(0));
  49     if (_numSrcRegs >= 2)
  50         ss << ", " << registerName(srcRegIdx(1));
  51     if (_numSrcRegs >= 3)
  52         ss << ", " << registerName(srcRegIdx(2));
  53     return ss.str();
  54 }
  55
  56 std::string
  57 CSROp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
  58 {
  59     std::stringstream ss;
  60     ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", ";
  61     auto data = CSRData.find(csr);
  62     if (data != CSRData.end())
  63         ss << data->second.name;
  64     else
  65         ss << "?? (" << std::hex << "0x" << csr << std::dec << ")";
  66     if (_numSrcRegs > 0)
  67         ss << ", " << registerName(srcRegIdx(0));
  68     else
  69         ss << uimm;
  70     return ss.str();
  71 }
  72
  73 std::string
  74 SystemOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
  75 {
  76     if (strcmp(mnemonic, "fence_vma") == 0) {
  77         std::stringstream ss;
  78         ss << mnemonic << ' ' << registerName(srcRegIdx(0)) << ", " <<
  79             registerName(srcRegIdx(1));
  80         return ss.str();
  81     }
  82
  83     return mnemonic;
  84 }
  85
  86 }