src/arch/riscv/insts/unknown.hh

   1 /*
   2  * Copyright (c) 2015 RISC-V Foundation
   3  * Copyright (c) 2017 The University of Virginia
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #ifndef __ARCH_RISCV_UNKNOWN_INST_HH__
  31 #define __ARCH_RISCV_UNKNOWN_INST_HH__
  32
  33 #include <memory>
  34 #include <string>
  35
  36 #include "arch/riscv/faults.hh"
  37 #include "arch/riscv/insts/bitfields.hh"
  38 #include "arch/riscv/insts/static_inst.hh"
  39 #include "cpu/exec_context.hh"
  40 #include "cpu/static_inst.hh"
  41
  42 namespace RiscvISA
  43 {
  44
  45 /**
  46  * Static instruction class for unknown (illegal) instructions.
  47  * These cause simulator termination if they are executed in a
  48  * non-speculative mode.  This is a leaf class.
  49  */
  50 class Unknown : public RiscvStaticInst
  51 {
  52   public:
  53     Unknown(MachInst _machInst)
  54         : RiscvStaticInst("unknown", _machInst, No_OpClass)
  55     {}
  56
  57     Fault
  58     execute(ExecContext *, Trace::InstRecord *) const override
  59     {
  60         return std::make_shared<UnknownInstFault>(machInst);
  61     }
  62
  63     std::string
  64     generateDisassembly(
  65             Addr pc, const Loader::SymbolTable *symtab) const override
  66     {
  67         return csprintf("unknown opcode %#02x", OPCODE);
  68     }
  69 };
  70
  71 }
  72
  73 #endif // __ARCH_RISCV_UNKNOWN_INST_HH__