src/arch/riscv/interrupts.hh

   1 /*
   2  * Copyright (c) 2011 Google
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 #ifndef __ARCH_RISCV_INTERRUPT_HH__
  32 #define __ARCH_RISCV_INTERRUPT_HH__
  33
  34 #include <bitset>
  35 #include <memory>
  36
  37 #include "arch/generic/interrupts.hh"
  38 #include "arch/riscv/faults.hh"
  39 #include "arch/riscv/registers.hh"
  40 #include "base/logging.hh"
  41 #include "cpu/thread_context.hh"
  42 #include "debug/Interrupt.hh"
  43 #include "params/RiscvInterrupts.hh"
  44 #include "sim/sim_object.hh"
  45
  46 class BaseCPU;
  47 class ThreadContext;
  48
  49 namespace RiscvISA {
  50
  51 /*
  52  * This is based on version 1.10 of the RISC-V privileged ISA reference,
  53  * chapter 3.1.14.
  54  */
  55 class Interrupts : public BaseInterrupts
  56 {
  57   private:
  58     BaseCPU * cpu;
  59     std::bitset<NumInterruptTypes> ip;
  60     std::bitset<NumInterruptTypes> ie;
  61
  62   public:
  63     typedef RiscvInterruptsParams Params;
  64
  65     const Params *
  66     params() const
  67     {
  68         return dynamic_cast<const Params *>(_params);
  69     }
  70
  71     Interrupts(Params * p) : BaseInterrupts(p), cpu(nullptr), ip(0), ie(0) {}
  72
  73     void setCPU(BaseCPU * _cpu) { cpu = _cpu; }
  74
  75     std::bitset<NumInterruptTypes>
  76     globalMask(ThreadContext *tc) const
  77     {
  78         INTERRUPT mask = 0;
  79         STATUS status = tc->readMiscReg(MISCREG_STATUS);
  80         if (status.mie)
  81             mask.mei = mask.mti = mask.msi = 1;
  82         if (status.sie)
  83             mask.sei = mask.sti = mask.ssi = 1;
  84         if (status.uie)
  85             mask.uei = mask.uti = mask.usi = 1;
  86         return std::bitset<NumInterruptTypes>(mask);
  87     }
  88
  89     bool checkInterrupt(int num) const { return ip[num] && ie[num]; }
  90     bool checkInterrupts(ThreadContext *tc) const
  91     {
  92         return (ip & ie & globalMask(tc)).any();
  93     }
  94
  95     Fault
  96     getInterrupt(ThreadContext *tc)
  97     {
  98         assert(checkInterrupts(tc));
  99         std::bitset<NumInterruptTypes> mask = globalMask(tc);
 100         for (int c = 0; c < NumInterruptTypes; c++)
 101             if (checkInterrupt(c) && mask[c])
 102                 return std::make_shared<InterruptFault>(c);
 103         return NoFault;
 104     }
 105
 106     void updateIntrInfo(ThreadContext *tc) {}
 107
 108     void
 109     post(int int_num, int index)
 110     {
 111         DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
 112         ip[int_num] = true;
 113     }
 114
 115     void
 116     clear(int int_num, int index)
 117     {
 118         DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
 119         ip[int_num] = false;
 120     }
 121
 122     void
 123     clearAll()
 124     {
 125         DPRINTF(Interrupt, "All interrupts cleared\n");
 126         ip = 0;
 127     }
 128
 129     uint64_t readIP() const { return (uint64_t)ip.to_ulong(); }
 130     uint64_t readIE() const { return (uint64_t)ie.to_ulong(); }
 131     void setIP(const uint64_t& val) { ip = val; }
 132     void setIE(const uint64_t& val) { ie = val; }
 133
 134     void
 135     serialize(CheckpointOut &cp) const
 136     {
 137         unsigned long ip_ulong = ip.to_ulong();
 138         unsigned long ie_ulong = ie.to_ulong();
 139         SERIALIZE_SCALAR(ip_ulong);
 140         SERIALIZE_SCALAR(ie_ulong);
 141     }
 142
 143     void
 144     unserialize(CheckpointIn &cp)
 145     {
 146         unsigned long ip_ulong;
 147         unsigned long ie_ulong;
 148         UNSERIALIZE_SCALAR(ip_ulong);
 149         ip = ip_ulong;
 150         UNSERIALIZE_SCALAR(ie_ulong);
 151         ie = ie_ulong;
 152     }
 153 };
 154
 155 } // namespace RiscvISA
 156
 157 #endif // __ARCH_RISCV_INTERRUPT_HH__