src/arch/riscv/interrupts.hh

   1 /*
   2  * Copyright (c) 2011 Google
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __ARCH_RISCV_INTERRUPT_HH__
  30 #define __ARCH_RISCV_INTERRUPT_HH__
  31
  32 #include <bitset>
  33 #include <memory>
  34
  35 #include "arch/generic/interrupts.hh"
  36 #include "arch/riscv/faults.hh"
  37 #include "arch/riscv/registers.hh"
  38 #include "base/logging.hh"
  39 #include "cpu/thread_context.hh"
  40 #include "debug/Interrupt.hh"
  41 #include "params/RiscvInterrupts.hh"
  42 #include "sim/sim_object.hh"
  43
  44 class BaseCPU;
  45 class ThreadContext;
  46
  47 namespace RiscvISA {
  48
  49 /*
  50  * This is based on version 1.10 of the RISC-V privileged ISA reference,
  51  * chapter 3.1.14.
  52  */
  53 class Interrupts : public BaseInterrupts
  54 {
  55   private:
  56     std::bitset<NumInterruptTypes> ip;
  57     std::bitset<NumInterruptTypes> ie;
  58
  59   public:
  60     typedef RiscvInterruptsParams Params;
  61
  62     const Params *
  63     params() const
  64     {
  65         return dynamic_cast<const Params *>(_params);
  66     }
  67
  68     Interrupts(Params * p) : BaseInterrupts(p), ip(0), ie(0) {}
  69
  70     std::bitset<NumInterruptTypes>
  71     globalMask() const
  72     {
  73         INTERRUPT mask = 0;
  74         STATUS status = tc->readMiscReg(MISCREG_STATUS);
  75         if (status.mie)
  76             mask.mei = mask.mti = mask.msi = 1;
  77         if (status.sie)
  78             mask.sei = mask.sti = mask.ssi = 1;
  79         if (status.uie)
  80             mask.uei = mask.uti = mask.usi = 1;
  81         return std::bitset<NumInterruptTypes>(mask);
  82     }
  83
  84     bool checkInterrupt(int num) const { return ip[num] && ie[num]; }
  85     bool checkInterrupts() const
  86     {
  87         return (ip & ie & globalMask()).any();
  88     }
  89
  90     Fault
  91     getInterrupt()
  92     {
  93         assert(checkInterrupts());
  94         std::bitset<NumInterruptTypes> mask = globalMask();
  95         for (int c = 0; c < NumInterruptTypes; c++)
  96             if (checkInterrupt(c) && mask[c])
  97                 return std::make_shared<InterruptFault>(c);
  98         return NoFault;
  99     }
 100
 101     void updateIntrInfo() {}
 102
 103     void
 104     post(int int_num, int index)
 105     {
 106         DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
 107         ip[int_num] = true;
 108     }
 109
 110     void
 111     clear(int int_num, int index)
 112     {
 113         DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
 114         ip[int_num] = false;
 115     }
 116
 117     void
 118     clearAll()
 119     {
 120         DPRINTF(Interrupt, "All interrupts cleared\n");
 121         ip = 0;
 122     }
 123
 124     uint64_t readIP() const { return (uint64_t)ip.to_ulong(); }
 125     uint64_t readIE() const { return (uint64_t)ie.to_ulong(); }
 126     void setIP(const uint64_t& val) { ip = val; }
 127     void setIE(const uint64_t& val) { ie = val; }
 128
 129     void
 130     serialize(CheckpointOut &cp) const
 131     {
 132         unsigned long ip_ulong = ip.to_ulong();
 133         unsigned long ie_ulong = ie.to_ulong();
 134         SERIALIZE_SCALAR(ip_ulong);
 135         SERIALIZE_SCALAR(ie_ulong);
 136     }
 137
 138     void
 139     unserialize(CheckpointIn &cp)
 140     {
 141         unsigned long ip_ulong;
 142         unsigned long ie_ulong;
 143         UNSERIALIZE_SCALAR(ip_ulong);
 144         ip = ip_ulong;
 145         UNSERIALIZE_SCALAR(ie_ulong);
 146         ie = ie_ulong;
 147     }
 148 };
 149
 150 } // namespace RiscvISA
 151
 152 #endif // __ARCH_RISCV_INTERRUPT_HH__