3 // Copyright (c) 2015 RISC-V Foundation
4 // Copyright (c) 2017 The University of Virginia
5 // All rights reserved.
7 // Redistribution and use in source and binary forms, with or without
8 // modification, are permitted provided that the following conditions are
9 // met: redistributions of source code must retain the above copyright
10 // notice, this list of conditions and the following disclaimer;
11 // redistributions in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the distribution;
14 // neither the name of the copyright holders nor the names of its
15 // contributors may be used to endorse or promote products derived from
16 // this software without specific prior written permission.
18 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 // Authors: Alec Roelke
32 ////////////////////////////////////////////////////////////////////
34 // The RISC-V ISA decoder
37 decode QUADRANT default Unknown::unknown() {
39 0x0: CUIOp::c_addi4spn({{
40 imm = CIMM8<1:1> << 2 |
46 fault = make_shared<IllegalInstFault>("zero instruction");
49 format CompressedLoad {
51 ldisp = CIMM3 << 3 | CIMM2 << 6;
58 ldisp = CIMM2<1:1> << 2 |
67 ldisp = CIMM3 << 3 | CIMM2 << 6;
74 format CompressedStore {
76 sdisp = CIMM3 << 3 | CIMM2 << 6;
83 sdisp = CIMM2<1:1> << 2 |
92 sdisp = CIMM3 << 3 | CIMM2 << 6;
100 0x1: decode COPCODE {
105 imm |= ~((uint64_t)0x1F);
107 if ((RC1 == 0) != (imm == 0)) {
109 fault = make_shared<IllegalInstFault>("source reg x0");
111 fault = make_shared<IllegalInstFault>("immediate = 0");
113 Rc1_sd = Rc1_sd + imm;
118 imm |= ~((uint64_t)0x1F);
121 Rc1_sd = (int32_t)Rc1_sd + imm;
126 imm |= ~((uint64_t)0x1F);
133 imm = CIMM5<4:4> << 4 |
138 imm |= ~((int64_t)0x1FF);
146 imm |= ~((uint64_t)0x1FFFF);
148 assert(RC1 != 0 && RC1 != 2);
154 0x4: decode CFUNCT2HIGH {
157 imm = CIMM5 | (CIMM1 << 5);
163 imm = CIMM5 | (CIMM1 << 5);
166 Rp1_sd = Rp1_sd >> imm;
171 imm |= ~((uint64_t)0x1F);
177 0x3: decode CFUNCT1 {
178 0x0: decode CFUNCT2LOW {
192 0x1: decode CFUNCT2LOW {
194 Rp1_sd = (int32_t)Rp1_sd - Rp2_sw;
197 Rp1_sd = (int32_t)Rp1_sd + Rp2_sw;
204 int64_t offset = CJUMPIMM<3:1> << 1 |
211 if (CJUMPIMM<10:10> > 0)
212 offset |= ~((int64_t)0x7FF);
214 }}, IsIndirectControl, IsUncondControl, IsCall);
217 int64_t offset = CIMM5<2:1> << 1 |
222 offset |= ~((int64_t)0xFF);
228 }}, IsDirectControl, IsCondControl);
230 int64_t offset = CIMM5<2:1> << 1 |
235 offset |= ~((int64_t)0xFF);
241 }}, IsDirectControl, IsCondControl);
244 0x2: decode COPCODE {
245 0x0: CUIOp::c_slli({{
246 imm = CIMM5 | (CIMM1 << 5);
252 format CompressedLoad {
254 ldisp = CIMM5<4:3> << 3 |
263 ldisp = CIMM5<4:2> << 2 |
273 ldisp = CIMM5<4:3> << 3 |
283 0x4: decode CFUNCT1 {
288 }}, IsIndirectControl, IsUncondControl, IsCall);
289 default: CROp::c_mv({{
295 0x0: SystemOp::c_ebreak({{
297 fault = make_shared<BreakpointFault>();
298 }}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
299 default: decode RC2 {
304 }}, IsIndirectControl, IsUncondControl, IsCall);
305 default: ROp::c_add({{
306 Rc1_sd = Rc1_sd + Rc2_sd;
311 format CompressedStore {
313 sdisp = CIMM6<5:3> << 3 |
321 sdisp = CIMM6<5:2> << 2 |
329 sdisp = CIMM6<5:3> << 3 |
339 0x00: decode FUNCT3 {
365 0x01: decode FUNCT3 {
368 Fd_bits = (uint64_t)Mem_uw;
376 0x03: decode FUNCT3 {
379 }}, IsNonSpeculative, IsMemBarrier, No_OpClass);
381 }}, IsNonSpeculative, IsSerializeAfter, No_OpClass);
385 0x04: decode FUNCT3 {
388 Rd_sd = Rs1_sd + imm;
394 Rd = (Rs1_sd < imm) ? 1 : 0;
397 Rd = (Rs1 < (uint64_t)imm) ? 1 : 0;
400 Rd = Rs1 ^ (uint64_t)imm;
407 Rd_sd = Rs1_sd >> SHAMT6;
411 Rd = Rs1 | (uint64_t)imm;
414 Rd = Rs1 & (uint64_t)imm;
423 0x06: decode FUNCT3 {
426 Rd_sd = (int32_t)Rs1 + (int32_t)imm;
429 Rd_sd = Rs1_sw << SHAMT5;
433 Rd = Rs1_uw >> SHAMT5;
436 Rd_sd = Rs1_sw >> SHAMT5;
442 0x08: decode FUNCT3 {
459 0x09: decode FUNCT3 {
462 Mem_uw = (uint32_t)Fs2_bits;
470 0x0b: decode FUNCT3 {
471 0x2: decode AMOFUNCT {
472 0x2: LoadReserved::lr_w({{
475 0x3: StoreCond::sc_w({{
479 }}, inst_flags=IsStoreConditional, mem_flags=LLSC);
481 0x0: amoadd_w({{Rt_sd = Mem_sw;}}, {{
482 Mem_sw = Rs2_sw + Rt_sd;
485 0x1: amoswap_w({{Rt_sd = Mem_sw;}}, {{
489 0x4: amoxor_w({{Rt_sd = Mem_sw;}}, {{
490 Mem_sw = Rs2_uw^Rt_sd;
493 0x8: amoor_w({{Rt_sd = Mem_sw;}}, {{
494 Mem_sw = Rs2_uw | Rt_sd;
497 0xc: amoand_w({{Rt_sd = Mem_sw;}}, {{
498 Mem_sw = Rs2_uw&Rt_sd;
501 0x10: amomin_w({{Rt_sd = Mem_sw;}}, {{
502 Mem_sw = min<int32_t>(Rs2_sw, Rt_sd);
505 0x14: amomax_w({{Rt_sd = Mem_sw;}}, {{
506 Mem_sw = max<int32_t>(Rs2_sw, Rt_sd);
509 0x18: amominu_w({{Rt_sd = Mem_sw;}}, {{
510 Mem_sw = min<uint32_t>(Rs2_uw, Rt_sd);
513 0x1c: amomaxu_w({{Rt_sd = Mem_sw;}}, {{
514 Mem_sw = max<uint32_t>(Rs2_uw, Rt_sd);
519 0x3: decode AMOFUNCT {
520 0x2: LoadReserved::lr_d({{
523 0x3: StoreCond::sc_d({{
527 }}, mem_flags=LLSC, inst_flags=IsStoreConditional);
529 0x0: amoadd_d({{Rt_sd = Mem_sd;}}, {{
530 Mem_sd = Rs2_sd + Rt_sd;
533 0x1: amoswap_d({{Rt = Mem;}}, {{
537 0x4: amoxor_d({{Rt = Mem;}}, {{
541 0x8: amoor_d({{Rt = Mem;}}, {{
545 0xc: amoand_d({{Rt = Mem;}}, {{
549 0x10: amomin_d({{Rt_sd = Mem_sd;}}, {{
550 Mem_sd = min(Rs2_sd, Rt_sd);
553 0x14: amomax_d({{Rt_sd = Mem_sd;}}, {{
554 Mem_sd = max(Rs2_sd, Rt_sd);
557 0x18: amominu_d({{Rt = Mem;}}, {{
561 0x1c: amomaxu_d({{Rt = Mem;}}, {{
568 0x0c: decode FUNCT3 {
572 Rd = Rs1_sd + Rs2_sd;
578 Rd = Rs1_sd - Rs2_sd;
583 Rd = Rs1 << Rs2<5:0>;
586 bool negate = (Rs1_sd < 0) != (Rs2_sd < 0);
588 uint64_t Rs1_lo = (uint32_t)abs(Rs1_sd);
589 uint64_t Rs1_hi = (uint64_t)abs(Rs1_sd) >> 32;
590 uint64_t Rs2_lo = (uint32_t)abs(Rs2_sd);
591 uint64_t Rs2_hi = (uint64_t)abs(Rs2_sd) >> 32;
593 uint64_t hi = Rs1_hi*Rs2_hi;
594 uint64_t mid1 = Rs1_hi*Rs2_lo;
595 uint64_t mid2 = Rs1_lo*Rs2_hi;
596 uint64_t lo = Rs2_lo*Rs1_lo;
597 uint64_t carry = ((uint64_t)(uint32_t)mid1
598 + (uint64_t)(uint32_t)mid2 + (lo >> 32)) >> 32;
604 Rd = negate ? ~res + (Rs1_sd*Rs2_sd == 0 ? 1 : 0)
610 Rd = (Rs1_sd < Rs2_sd) ? 1 : 0;
613 bool negate = Rs1_sd < 0;
614 uint64_t Rs1_lo = (uint32_t)abs(Rs1_sd);
615 uint64_t Rs1_hi = (uint64_t)abs(Rs1_sd) >> 32;
616 uint64_t Rs2_lo = (uint32_t)Rs2;
617 uint64_t Rs2_hi = Rs2 >> 32;
619 uint64_t hi = Rs1_hi*Rs2_hi;
620 uint64_t mid1 = Rs1_hi*Rs2_lo;
621 uint64_t mid2 = Rs1_lo*Rs2_hi;
622 uint64_t lo = Rs1_lo*Rs2_lo;
623 uint64_t carry = ((uint64_t)(uint32_t)mid1
624 + (uint64_t)(uint32_t)mid2 + (lo >> 32)) >> 32;
630 Rd = negate ? ~res + (Rs1_sd*Rs2 == 0 ? 1 : 0) : res;
635 Rd = (Rs1 < Rs2) ? 1 : 0;
638 uint64_t Rs1_lo = (uint32_t)Rs1;
639 uint64_t Rs1_hi = Rs1 >> 32;
640 uint64_t Rs2_lo = (uint32_t)Rs2;
641 uint64_t Rs2_hi = Rs2 >> 32;
643 uint64_t hi = Rs1_hi*Rs2_hi;
644 uint64_t mid1 = Rs1_hi*Rs2_lo;
645 uint64_t mid2 = Rs1_lo*Rs2_hi;
646 uint64_t lo = Rs1_lo*Rs2_lo;
647 uint64_t carry = ((uint64_t)(uint32_t)mid1
648 + (uint64_t)(uint32_t)mid2 + (lo >> 32)) >> 32;
650 Rd = hi + (mid1 >> 32) + (mid2 >> 32) + carry;
660 } else if (Rs1_sd == numeric_limits<int64_t>::min()
662 Rd_sd = numeric_limits<int64_t>::min();
664 Rd_sd = Rs1_sd/Rs2_sd;
670 Rd = Rs1 >> Rs2<5:0>;
674 Rd = numeric_limits<uint64_t>::max();
680 Rd_sd = Rs1_sd >> Rs2<5:0>;
690 } else if (Rs1_sd == numeric_limits<int64_t>::min()
717 0x0e: decode FUNCT3 {
721 Rd_sd = Rs1_sw + Rs2_sw;
724 Rd_sd = (int32_t)(Rs1_sw*Rs2_sw);
727 Rd_sd = Rs1_sw - Rs2_sw;
731 Rd_sd = Rs1_sw << Rs2<4:0>;
736 } else if (Rs1_sw == numeric_limits<int32_t>::min()
738 Rd_sd = numeric_limits<int32_t>::min();
740 Rd_sd = Rs1_sw/Rs2_sw;
745 Rd_uw = Rs1_uw >> Rs2<4:0>;
749 Rd_sd = numeric_limits<IntReg>::max();
751 Rd_sd = (int32_t)(Rs1_uw/Rs2_uw);
755 Rd_sd = Rs1_sw >> Rs2<4:0>;
761 } else if (Rs1_sw == numeric_limits<int32_t>::min()
765 Rd_sd = Rs1_sw%Rs2_sw;
770 Rd_sd = (int32_t)Rs1_uw;
772 Rd_sd = (int32_t)(Rs1_uw%Rs2_uw);
779 0x10: decode FUNCT2 {
782 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
783 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
784 float fs3 = reinterpret_cast<float&>(temp = Fs3_bits);
787 if (isnan(fs1) || isnan(fs2) || isnan(fs3)) {
788 if (issignalingnan(fs1) || issignalingnan(fs2)
789 || issignalingnan(fs3)) {
790 FFLAGS |= FloatInvalid;
792 fd = numeric_limits<float>::quiet_NaN();
793 } else if (isinf(fs1) || isinf(fs2) ||
795 if (signbit(fs1) == signbit(fs2)
797 fd = numeric_limits<float>::infinity();
798 } else if (signbit(fs1) != signbit(fs2)
800 fd = -numeric_limits<float>::infinity();
801 } else { // Fs3_sf is infinity
807 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
810 if (isnan(Fs1) || isnan(Fs2) || isnan(Fs3)) {
811 if (issignalingnan(Fs1) || issignalingnan(Fs2)
812 || issignalingnan(Fs3)) {
813 FFLAGS |= FloatInvalid;
815 Fd = numeric_limits<double>::quiet_NaN();
816 } else if (isinf(Fs1) || isinf(Fs2) ||
818 if (signbit(Fs1) == signbit(Fs2)
820 Fd = numeric_limits<double>::infinity();
821 } else if (signbit(Fs1) != signbit(Fs2)
823 Fd = -numeric_limits<double>::infinity();
832 0x11: decode FUNCT2 {
835 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
836 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
837 float fs3 = reinterpret_cast<float&>(temp = Fs3_bits);
840 if (isnan(fs1) || isnan(fs2) || isnan(fs3)) {
841 if (issignalingnan(fs1) || issignalingnan(fs2)
842 || issignalingnan(fs3)) {
843 FFLAGS |= FloatInvalid;
845 fd = numeric_limits<float>::quiet_NaN();
846 } else if (isinf(fs1) || isinf(fs2) ||
848 if (signbit(fs1) == signbit(fs2)
850 fd = numeric_limits<float>::infinity();
851 } else if (signbit(fs1) != signbit(fs2)
853 fd = -numeric_limits<float>::infinity();
854 } else { // Fs3_sf is infinity
860 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
863 if (isnan(Fs1) || isnan(Fs2) || isnan(Fs3)) {
864 if (issignalingnan(Fs1) || issignalingnan(Fs2)
865 || issignalingnan(Fs3)) {
866 FFLAGS |= FloatInvalid;
868 Fd = numeric_limits<double>::quiet_NaN();
869 } else if (isinf(Fs1) || isinf(Fs2) ||
871 if (signbit(Fs1) == signbit(Fs2)
873 Fd = numeric_limits<double>::infinity();
874 } else if (signbit(Fs1) != signbit(Fs2)
876 Fd = -numeric_limits<double>::infinity();
885 0x12: decode FUNCT2 {
888 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
889 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
890 float fs3 = reinterpret_cast<float&>(temp = Fs3_bits);
893 if (isnan(fs1) || isnan(fs2) || isnan(fs3)) {
894 if (issignalingnan(fs1) || issignalingnan(fs2)
895 || issignalingnan(fs3)) {
896 FFLAGS |= FloatInvalid;
898 fd = numeric_limits<float>::quiet_NaN();
899 } else if (isinf(fs1) || isinf(fs2) ||
901 if (signbit(fs1) == signbit(fs2)
903 fd = -numeric_limits<float>::infinity();
904 } else if (signbit(fs1) != signbit(fs2)
906 fd = numeric_limits<float>::infinity();
907 } else { // Fs3_sf is infinity
911 fd = -(fs1*fs2 - fs3);
913 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
916 if (isnan(Fs1) || isnan(Fs2) || isnan(Fs3)) {
917 if (issignalingnan(Fs1) || issignalingnan(Fs2)
918 || issignalingnan(Fs3)) {
919 FFLAGS |= FloatInvalid;
921 Fd = numeric_limits<double>::quiet_NaN();
922 } else if (isinf(Fs1) || isinf(Fs2)
924 if (signbit(Fs1) == signbit(Fs2)
926 Fd = -numeric_limits<double>::infinity();
927 } else if (signbit(Fs1) != signbit(Fs2)
929 Fd = numeric_limits<double>::infinity();
934 Fd = -(Fs1*Fs2 - Fs3);
938 0x13: decode FUNCT2 {
941 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
942 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
943 float fs3 = reinterpret_cast<float&>(temp = Fs3_bits);
946 if (isnan(fs1) || isnan(fs2) || isnan(fs3)) {
947 if (issignalingnan(fs1) || issignalingnan(fs2)
948 || issignalingnan(fs3)) {
949 FFLAGS |= FloatInvalid;
951 fd = numeric_limits<float>::quiet_NaN();
952 } else if (isinf(fs1) || isinf(fs2) ||
954 if (signbit(fs1) == signbit(fs2)
956 fd = -numeric_limits<float>::infinity();
957 } else if (signbit(fs1) != signbit(fs2)
959 fd = numeric_limits<float>::infinity();
960 } else { // Fs3_sf is infinity
964 fd = -(fs1*fs2 + fs3);
966 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
969 if (isnan(Fs1) || isnan(Fs2) || isnan(Fs3)) {
970 if (issignalingnan(Fs1) || issignalingnan(Fs2)
971 || issignalingnan(Fs3)) {
972 FFLAGS |= FloatInvalid;
974 Fd = numeric_limits<double>::quiet_NaN();
975 } else if (isinf(Fs1) || isinf(Fs2) ||
977 if (signbit(Fs1) == signbit(Fs2)
979 Fd = -numeric_limits<double>::infinity();
980 } else if (signbit(Fs1) != signbit(Fs2)
982 Fd = numeric_limits<double>::infinity();
987 Fd = -(Fs1*Fs2 + Fs3);
991 0x14: decode FUNCT7 {
994 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
995 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
998 if (isnan(fs1) || isnan(fs2)) {
999 if (issignalingnan(fs1) || issignalingnan(fs2)) {
1000 FFLAGS |= FloatInvalid;
1002 fd = numeric_limits<float>::quiet_NaN();
1006 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1009 if (isnan(Fs1) || isnan(Fs2)) {
1010 if (issignalingnan(Fs1) || issignalingnan(Fs2)) {
1011 FFLAGS |= FloatInvalid;
1013 Fd = numeric_limits<double>::quiet_NaN();
1020 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1021 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1024 if (isnan(fs1) || isnan(fs2)) {
1025 if (issignalingnan(fs1) || issignalingnan(fs2)) {
1026 FFLAGS |= FloatInvalid;
1028 fd = numeric_limits<float>::quiet_NaN();
1032 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1035 if (isnan(Fs1) || isnan(Fs2)) {
1036 if (issignalingnan(Fs1) || issignalingnan(Fs2)) {
1037 FFLAGS |= FloatInvalid;
1039 Fd = numeric_limits<double>::quiet_NaN();
1046 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1047 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1050 if (isnan(fs1) || isnan(fs2)) {
1051 if (issignalingnan(fs1) || issignalingnan(fs2)) {
1052 FFLAGS |= FloatInvalid;
1054 fd = numeric_limits<float>::quiet_NaN();
1058 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1061 if (isnan(Fs1) || isnan(Fs2)) {
1062 if (issignalingnan(Fs1) || issignalingnan(Fs2)) {
1063 FFLAGS |= FloatInvalid;
1065 Fd = numeric_limits<double>::quiet_NaN();
1072 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1073 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1076 if (isnan(fs1) || isnan(fs2)) {
1077 if (issignalingnan(fs1) || issignalingnan(fs2)) {
1078 FFLAGS |= FloatInvalid;
1080 fd = numeric_limits<float>::quiet_NaN();
1084 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1087 if (isnan(Fs1) || isnan(Fs2)) {
1088 if (issignalingnan(Fs1) || issignalingnan(Fs2)) {
1089 FFLAGS |= FloatInvalid;
1091 Fd = numeric_limits<double>::quiet_NaN();
1096 0x10: decode ROUND_MODE {
1099 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1100 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1103 if (issignalingnan(fs1)) {
1104 fd = numeric_limits<float>::signaling_NaN();
1105 feclearexcept(FE_INVALID);
1107 fd = copysign(fs1, fs2);
1109 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1113 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1114 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1117 if (issignalingnan(fs1)) {
1118 fd = numeric_limits<float>::signaling_NaN();
1119 feclearexcept(FE_INVALID);
1121 fd = copysign(fs1, -fs2);
1123 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1127 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1128 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1131 if (issignalingnan(fs1)) {
1132 fd = numeric_limits<float>::signaling_NaN();
1133 feclearexcept(FE_INVALID);
1135 fd = fs1*(signbit(fs2) ? -1.0 : 1.0);
1137 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1140 0x11: decode ROUND_MODE {
1142 if (issignalingnan(Fs1)) {
1143 Fd = numeric_limits<double>::signaling_NaN();
1144 feclearexcept(FE_INVALID);
1146 Fd = copysign(Fs1, Fs2);
1150 if (issignalingnan(Fs1)) {
1151 Fd = numeric_limits<double>::signaling_NaN();
1152 feclearexcept(FE_INVALID);
1154 Fd = copysign(Fs1, -Fs2);
1158 if (issignalingnan(Fs1)) {
1159 Fd = numeric_limits<double>::signaling_NaN();
1160 feclearexcept(FE_INVALID);
1162 Fd = Fs1*(signbit(Fs2) ? -1.0 : 1.0);
1166 0x14: decode ROUND_MODE {
1169 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1170 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1173 if (issignalingnan(fs2)) {
1175 FFLAGS |= FloatInvalid;
1176 } else if (issignalingnan(fs1)) {
1178 FFLAGS |= FloatInvalid;
1180 fd = fmin(fs1, fs2);
1182 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1186 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1187 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1190 if (issignalingnan(fs2)) {
1192 FFLAGS |= FloatInvalid;
1193 } else if (issignalingnan(fs1)) {
1195 FFLAGS |= FloatInvalid;
1197 fd = fmax(fs1, fs2);
1199 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1202 0x15: decode ROUND_MODE {
1204 if (issignalingnan(Fs2)) {
1206 FFLAGS |= FloatInvalid;
1207 } else if (issignalingnan(Fs1)) {
1209 FFLAGS |= FloatInvalid;
1211 Fd = fmin(Fs1, Fs2);
1215 if (issignalingnan(Fs2)) {
1217 FFLAGS |= FloatInvalid;
1218 } else if (issignalingnan(Fs1)) {
1220 FFLAGS |= FloatInvalid;
1222 Fd = fmax(Fs1, Fs2);
1227 assert(CONV_SGN == 1);
1229 if (issignalingnan(Fs1)) {
1230 fd = numeric_limits<float>::quiet_NaN();
1231 FFLAGS |= FloatInvalid;
1235 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1238 assert(CONV_SGN == 0);
1240 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1242 if (issignalingnan(fs1)) {
1243 Fd = numeric_limits<double>::quiet_NaN();
1244 FFLAGS |= FloatInvalid;
1252 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1255 if (issignalingnan(Fs1_sf)) {
1256 FFLAGS |= FloatInvalid;
1259 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1265 0x50: decode ROUND_MODE {
1268 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1269 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1271 if (isnan(fs1) || isnan(fs2)) {
1272 FFLAGS |= FloatInvalid;
1275 Rd = fs1 <= fs2 ? 1 : 0;
1280 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1281 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1283 if (isnan(fs1) || isnan(fs2)) {
1284 FFLAGS |= FloatInvalid;
1287 Rd = fs1 < fs2 ? 1 : 0;
1292 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1293 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1295 if (issignalingnan(fs1) || issignalingnan(fs2)) {
1296 FFLAGS |= FloatInvalid;
1298 Rd = fs1 == fs2 ? 1 : 0;
1301 0x51: decode ROUND_MODE {
1303 if (isnan(Fs1) || isnan(Fs2)) {
1304 FFLAGS |= FloatInvalid;
1307 Rd = Fs1 <= Fs2 ? 1 : 0;
1311 if (isnan(Fs1) || isnan(Fs2)) {
1312 FFLAGS |= FloatInvalid;
1315 Rd = Fs1 < Fs2 ? 1 : 0;
1319 if (issignalingnan(Fs1) || issignalingnan(Fs2)) {
1320 FFLAGS |= FloatInvalid;
1322 Rd = Fs1 == Fs2 ? 1 : 0;
1325 0x60: decode CONV_SGN {
1328 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1331 Rd_sd = numeric_limits<int32_t>::max();
1332 FFLAGS |= FloatInvalid;
1334 Rd_sd = (int32_t)fs1;
1335 if (fetestexcept(FE_INVALID)) {
1337 Rd_sd = numeric_limits<int32_t>::min();
1339 Rd_sd = numeric_limits<int32_t>::max();
1341 feclearexcept(FE_INEXACT);
1347 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1351 FFLAGS |= FloatInvalid;
1354 if (fetestexcept(FE_INVALID)) {
1355 Rd = numeric_limits<uint64_t>::max();
1356 feclearexcept(FE_INEXACT);
1362 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1365 Rd_sd = numeric_limits<int64_t>::max();
1366 FFLAGS |= FloatInvalid;
1368 Rd_sd = (int64_t)fs1;
1369 if (fetestexcept(FE_INVALID)) {
1371 Rd_sd = numeric_limits<int64_t>::min();
1373 Rd_sd = numeric_limits<int64_t>::max();
1375 feclearexcept(FE_INEXACT);
1381 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1385 FFLAGS |= FloatInvalid;
1388 if (fetestexcept(FE_INVALID)) {
1389 Rd = numeric_limits<uint64_t>::max();
1390 feclearexcept(FE_INEXACT);
1395 0x61: decode CONV_SGN {
1397 Rd_sd = (int32_t)Fs1;
1398 if (fetestexcept(FE_INVALID)) {
1400 Rd_sd = numeric_limits<int32_t>::min();
1402 Rd_sd = numeric_limits<int32_t>::max();
1404 feclearexcept(FE_INEXACT);
1410 FFLAGS |= FloatInvalid;
1413 if (fetestexcept(FE_INVALID)) {
1414 Rd = numeric_limits<uint64_t>::max();
1415 feclearexcept(FE_INEXACT);
1421 if (fetestexcept(FE_INVALID)) {
1423 Rd_sd = numeric_limits<int64_t>::min();
1425 Rd_sd = numeric_limits<int64_t>::max();
1427 feclearexcept(FE_INEXACT);
1433 FFLAGS |= FloatInvalid;
1436 if (fetestexcept(FE_INVALID)) {
1437 Rd = numeric_limits<uint64_t>::max();
1438 feclearexcept(FE_INEXACT);
1443 0x68: decode CONV_SGN {
1445 float temp = (float)Rs1_sw;
1446 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(temp);
1449 float temp = (float)Rs1_uw;
1450 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(temp);
1453 float temp = (float)Rs1_sd;
1454 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(temp);
1457 float temp = (float)Rs1;
1458 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(temp);
1461 0x69: decode CONV_SGN {
1463 Fd = (double)Rs1_sw;
1466 Fd = (double)Rs1_uw;
1469 Fd = (double)Rs1_sd;
1475 0x70: decode ROUND_MODE {
1477 Rd = (uint32_t)Fs1_bits;
1478 if ((Rd&0x80000000) != 0) {
1479 Rd |= (0xFFFFFFFFULL << 32);
1484 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1485 switch (fpclassify(fs1)) {
1494 if (issignalingnan(fs1)) {
1522 panic("Unknown classification for operand.");
1527 0x71: decode ROUND_MODE {
1532 switch (fpclassify(Fs1)) {
1541 if (issignalingnan(Fs1)) {
1569 panic("Unknown classification for operand.");
1575 Fd_bits = (uint64_t)Rs1_uw;
1583 0x18: decode FUNCT3 {
1591 }}, IsDirectControl, IsCondControl);
1598 }}, IsDirectControl, IsCondControl);
1600 if (Rs1_sd < Rs2_sd) {
1605 }}, IsDirectControl, IsCondControl);
1607 if (Rs1_sd >= Rs2_sd) {
1612 }}, IsDirectControl, IsCondControl);
1619 }}, IsDirectControl, IsCondControl);
1626 }}, IsDirectControl, IsCondControl);
1630 0x19: decode FUNCT3 {
1633 NPC = (imm + Rs1) & (~0x1);
1634 }}, IsIndirectControl, IsUncondControl, IsCall);
1640 }}, IsDirectControl, IsUncondControl, IsCall);
1642 0x1c: decode FUNCT3 {
1644 0x0: decode FUNCT12 {
1646 fault = make_shared<SyscallFault>();
1647 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall,
1650 fault = make_shared<BreakpointFault>();
1651 }}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
1653 fault = make_shared<UnimplementedFault>("eret");
1659 Rd = xc->readMiscReg(csr);
1660 xc->setMiscReg(csr, Rs1);
1661 }}, IsNonSpeculative, No_OpClass);
1663 Rd = xc->readMiscReg(csr);
1665 xc->setMiscReg(csr, Rd | Rs1);
1667 }}, IsNonSpeculative, No_OpClass);
1669 Rd = xc->readMiscReg(csr);
1671 xc->setMiscReg(csr, Rd & ~Rs1);
1673 }}, IsNonSpeculative, No_OpClass);
1675 Rd = xc->readMiscReg(csr);
1676 xc->setMiscReg(csr, uimm);
1677 }}, IsNonSpeculative, No_OpClass);
1679 Rd = xc->readMiscReg(csr);
1681 xc->setMiscReg(csr, Rd | uimm);
1683 }}, IsNonSpeculative, No_OpClass);
1685 Rd = xc->readMiscReg(csr);
1687 xc->setMiscReg(csr, Rd & ~uimm);
1689 }}, IsNonSpeculative, No_OpClass);