3 // Copyright (c) 2015 RISC-V Foundation
4 // Copyright (c) 2017 The University of Virginia
5 // All rights reserved.
7 // Redistribution and use in source and binary forms, with or without
8 // modification, are permitted provided that the following conditions are
9 // met: redistributions of source code must retain the above copyright
10 // notice, this list of conditions and the following disclaimer;
11 // redistributions in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the distribution;
14 // neither the name of the copyright holders nor the names of its
15 // contributors may be used to endorse or promote products derived from
16 // this software without specific prior written permission.
18 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 // Authors: Alec Roelke
32 ////////////////////////////////////////////////////////////////////
34 // The RISC-V ISA decoder
37 decode QUADRANT default Unknown::unknown() {
39 0x0: CUIOp::c_addi4spn({{
40 imm = CIMM8<1:1> << 2 |
46 fault = make_shared<IllegalInstFault>("zero instruction");
49 format CompressedLoad {
51 offset = CIMM3 << 3 | CIMM2 << 6;
58 offset = CIMM2<1:1> << 2 |
67 offset = CIMM3 << 3 | CIMM2 << 6;
74 format CompressedStore {
76 offset = CIMM3 << 3 | CIMM2 << 6;
83 offset = CIMM2<1:1> << 2 |
92 offset = CIMM3 << 3 | CIMM2 << 6;
100 0x1: decode COPCODE {
105 imm |= ~((uint64_t)0x1F);
107 if ((RC1 == 0) != (imm == 0)) {
109 fault = make_shared<IllegalInstFault>("source reg x0");
111 fault = make_shared<IllegalInstFault>("immediate = 0");
113 Rc1_sd = Rc1_sd + imm;
118 imm |= ~((uint64_t)0x1F);
121 Rc1_sd = (int32_t)Rc1_sd + imm;
126 imm |= ~((uint64_t)0x1F);
133 imm = CIMM5<4:4> << 4 |
138 imm |= ~((int64_t)0x1FF);
146 imm |= ~((uint64_t)0x1FFFF);
148 assert(RC1 != 0 && RC1 != 2);
154 0x4: decode CFUNCT2HIGH {
157 imm = CIMM5 | (CIMM1 << 5);
163 imm = CIMM5 | (CIMM1 << 5);
166 Rp1_sd = Rp1_sd >> imm;
171 imm |= ~((uint64_t)0x1F);
177 0x3: decode CFUNCT1 {
178 0x0: decode CFUNCT2LOW {
192 0x1: decode CFUNCT2LOW {
194 Rp1_sd = (int32_t)Rp1_sd - Rp2_sw;
197 Rp1_sd = (int32_t)Rp1_sd + Rp2_sw;
204 int64_t offset = CJUMPIMM<3:1> << 1 |
211 if (CJUMPIMM<10:10> > 0)
212 offset |= ~((int64_t)0x7FF);
214 }}, IsIndirectControl, IsUncondControl, IsCall);
217 int64_t offset = CIMM5<2:1> << 1 |
222 offset |= ~((int64_t)0xFF);
228 }}, IsDirectControl, IsCondControl);
230 int64_t offset = CIMM5<2:1> << 1 |
235 offset |= ~((int64_t)0xFF);
241 }}, IsDirectControl, IsCondControl);
244 0x2: decode COPCODE {
245 0x0: CUIOp::c_slli({{
246 imm = CIMM5 | (CIMM1 << 5);
252 format CompressedLoad {
254 offset = CIMM5<4:3> << 3 |
263 offset = CIMM5<4:2> << 2 |
273 offset = CIMM5<4:3> << 3 |
283 0x4: decode CFUNCT1 {
288 }}, IsIndirectControl, IsUncondControl, IsCall);
289 default: CROp::c_mv({{
295 0x0: SystemOp::c_ebreak({{
297 fault = make_shared<BreakpointFault>();
298 }}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
299 default: decode RC2 {
304 }}, IsIndirectControl, IsUncondControl, IsCall);
305 default: ROp::c_add({{
306 Rc1_sd = Rc1_sd + Rc2_sd;
311 format CompressedStore {
313 offset = CIMM6<5:3> << 3 |
321 offset = CIMM6<5:2> << 2 |
329 offset = CIMM6<5:3> << 3 |
339 0x00: decode FUNCT3 {
365 0x01: decode FUNCT3 {
368 Fd_bits = (uint64_t)Mem_uw;
376 0x03: decode FUNCT3 {
379 }}, IsNonSpeculative, IsMemBarrier, No_OpClass);
381 }}, IsNonSpeculative, IsSerializeAfter, No_OpClass);
385 0x04: decode FUNCT3 {
388 Rd_sd = Rs1_sd + imm;
394 Rd = (Rs1_sd < imm) ? 1 : 0;
397 Rd = (Rs1 < (uint64_t)imm) ? 1 : 0;
400 Rd = Rs1 ^ (uint64_t)imm;
407 Rd_sd = Rs1_sd >> SHAMT6;
411 Rd = Rs1 | (uint64_t)imm;
414 Rd = Rs1 & (uint64_t)imm;
423 0x06: decode FUNCT3 {
426 Rd_sd = (int32_t)Rs1 + (int32_t)imm;
429 Rd_sd = Rs1_sw << SHAMT5;
433 Rd = Rs1_uw >> SHAMT5;
436 Rd_sd = Rs1_sw >> SHAMT5;
442 0x08: decode FUNCT3 {
459 0x09: decode FUNCT3 {
462 Mem_uw = (uint32_t)Fs2_bits;
470 0x0b: decode FUNCT3 {
471 0x2: decode AMOFUNCT {
472 0x2: LoadReserved::lr_w({{
475 0x3: StoreCond::sc_w({{
479 }}, inst_flags=IsStoreConditional, mem_flags=LLSC);
481 0x0: amoadd_w({{Rt_sd = Mem_sw;}}, {{
482 Mem_sw = Rs2_sw + Rt_sd;
485 0x1: amoswap_w({{Rt_sd = Mem_sw;}}, {{
489 0x4: amoxor_w({{Rt_sd = Mem_sw;}}, {{
490 Mem_sw = Rs2_uw^Rt_sd;
493 0x8: amoor_w({{Rt_sd = Mem_sw;}}, {{
494 Mem_sw = Rs2_uw | Rt_sd;
497 0xc: amoand_w({{Rt_sd = Mem_sw;}}, {{
498 Mem_sw = Rs2_uw&Rt_sd;
501 0x10: amomin_w({{Rt_sd = Mem_sw;}}, {{
502 Mem_sw = min<int32_t>(Rs2_sw, Rt_sd);
505 0x14: amomax_w({{Rt_sd = Mem_sw;}}, {{
506 Mem_sw = max<int32_t>(Rs2_sw, Rt_sd);
509 0x18: amominu_w({{Rt_sd = Mem_sw;}}, {{
510 Mem_sw = min<uint32_t>(Rs2_uw, Rt_sd);
513 0x1c: amomaxu_w({{Rt_sd = Mem_sw;}}, {{
514 Mem_sw = max<uint32_t>(Rs2_uw, Rt_sd);
519 0x3: decode AMOFUNCT {
520 0x2: LoadReserved::lr_d({{
523 0x3: StoreCond::sc_d({{
527 }}, mem_flags=LLSC, inst_flags=IsStoreConditional);
529 0x0: amoadd_d({{Rt_sd = Mem_sd;}}, {{
530 Mem_sd = Rs2_sd + Rt_sd;
533 0x1: amoswap_d({{Rt = Mem;}}, {{
537 0x4: amoxor_d({{Rt = Mem;}}, {{
541 0x8: amoor_d({{Rt = Mem;}}, {{
545 0xc: amoand_d({{Rt = Mem;}}, {{
549 0x10: amomin_d({{Rt_sd = Mem_sd;}}, {{
550 Mem_sd = min(Rs2_sd, Rt_sd);
553 0x14: amomax_d({{Rt_sd = Mem_sd;}}, {{
554 Mem_sd = max(Rs2_sd, Rt_sd);
557 0x18: amominu_d({{Rt = Mem;}}, {{
561 0x1c: amomaxu_d({{Rt = Mem;}}, {{
568 0x0c: decode FUNCT3 {
572 Rd = Rs1_sd + Rs2_sd;
578 Rd = Rs1_sd - Rs2_sd;
583 Rd = Rs1 << Rs2<5:0>;
586 bool negate = (Rs1_sd < 0) != (Rs2_sd < 0);
588 uint64_t Rs1_lo = (uint32_t)abs(Rs1_sd);
589 uint64_t Rs1_hi = (uint64_t)abs(Rs1_sd) >> 32;
590 uint64_t Rs2_lo = (uint32_t)abs(Rs2_sd);
591 uint64_t Rs2_hi = (uint64_t)abs(Rs2_sd) >> 32;
593 uint64_t hi = Rs1_hi*Rs2_hi;
594 uint64_t mid1 = Rs1_hi*Rs2_lo;
595 uint64_t mid2 = Rs1_lo*Rs2_hi;
596 uint64_t lo = Rs2_lo*Rs1_lo;
597 uint64_t carry = ((uint64_t)(uint32_t)mid1
598 + (uint64_t)(uint32_t)mid2 + (lo >> 32)) >> 32;
604 Rd = negate ? ~res + (Rs1_sd*Rs2_sd == 0 ? 1 : 0)
610 Rd = (Rs1_sd < Rs2_sd) ? 1 : 0;
613 bool negate = Rs1_sd < 0;
614 uint64_t Rs1_lo = (uint32_t)abs(Rs1_sd);
615 uint64_t Rs1_hi = (uint64_t)abs(Rs1_sd) >> 32;
616 uint64_t Rs2_lo = (uint32_t)Rs2;
617 uint64_t Rs2_hi = Rs2 >> 32;
619 uint64_t hi = Rs1_hi*Rs2_hi;
620 uint64_t mid1 = Rs1_hi*Rs2_lo;
621 uint64_t mid2 = Rs1_lo*Rs2_hi;
622 uint64_t lo = Rs1_lo*Rs2_lo;
623 uint64_t carry = ((uint64_t)(uint32_t)mid1
624 + (uint64_t)(uint32_t)mid2 + (lo >> 32)) >> 32;
630 Rd = negate ? ~res + (Rs1_sd*Rs2 == 0 ? 1 : 0) : res;
635 Rd = (Rs1 < Rs2) ? 1 : 0;
638 uint64_t Rs1_lo = (uint32_t)Rs1;
639 uint64_t Rs1_hi = Rs1 >> 32;
640 uint64_t Rs2_lo = (uint32_t)Rs2;
641 uint64_t Rs2_hi = Rs2 >> 32;
643 uint64_t hi = Rs1_hi*Rs2_hi;
644 uint64_t mid1 = Rs1_hi*Rs2_lo;
645 uint64_t mid2 = Rs1_lo*Rs2_hi;
646 uint64_t lo = Rs1_lo*Rs2_lo;
647 uint64_t carry = ((uint64_t)(uint32_t)mid1
648 + (uint64_t)(uint32_t)mid2 + (lo >> 32)) >> 32;
650 Rd = hi + (mid1 >> 32) + (mid2 >> 32) + carry;
660 } else if (Rs1_sd == numeric_limits<int64_t>::min()
662 Rd_sd = numeric_limits<int64_t>::min();
664 Rd_sd = Rs1_sd/Rs2_sd;
670 Rd = Rs1 >> Rs2<5:0>;
674 Rd = numeric_limits<uint64_t>::max();
680 Rd_sd = Rs1_sd >> Rs2<5:0>;
690 } else if (Rs1_sd == numeric_limits<int64_t>::min()
717 0x0e: decode FUNCT3 {
721 Rd_sd = Rs1_sw + Rs2_sw;
724 Rd_sd = (int32_t)(Rs1_sw*Rs2_sw);
727 Rd_sd = Rs1_sw - Rs2_sw;
731 Rd_sd = Rs1_sw << Rs2<4:0>;
736 } else if (Rs1_sw == numeric_limits<int32_t>::min()
738 Rd_sd = numeric_limits<int32_t>::min();
740 Rd_sd = Rs1_sw/Rs2_sw;
745 Rd_uw = Rs1_uw >> Rs2<4:0>;
749 Rd_sd = numeric_limits<IntReg>::max();
751 Rd_sd = (int32_t)(Rs1_uw/Rs2_uw);
755 Rd_sd = Rs1_sw >> Rs2<4:0>;
761 } else if (Rs1_sw == numeric_limits<int32_t>::min()
765 Rd_sd = Rs1_sw%Rs2_sw;
770 Rd_sd = (int32_t)Rs1_uw;
772 Rd_sd = (int32_t)(Rs1_uw%Rs2_uw);
779 0x10: decode FUNCT2 {
782 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
783 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
784 float fs3 = reinterpret_cast<float&>(temp = Fs3_bits);
787 if (std::isnan(fs1) || std::isnan(fs2) ||
789 if (issignalingnan(fs1) || issignalingnan(fs2)
790 || issignalingnan(fs3)) {
791 FFLAGS |= FloatInvalid;
793 fd = numeric_limits<float>::quiet_NaN();
794 } else if (std::isinf(fs1) || std::isinf(fs2) ||
796 if (signbit(fs1) == signbit(fs2)
797 && !std::isinf(fs3)) {
798 fd = numeric_limits<float>::infinity();
799 } else if (signbit(fs1) != signbit(fs2)
800 && !std::isinf(fs3)) {
801 fd = -numeric_limits<float>::infinity();
802 } else { // Fs3_sf is infinity
808 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
811 if (std::isnan(Fs1) || std::isnan(Fs2) ||
813 if (issignalingnan(Fs1) || issignalingnan(Fs2)
814 || issignalingnan(Fs3)) {
815 FFLAGS |= FloatInvalid;
817 Fd = numeric_limits<double>::quiet_NaN();
818 } else if (std::isinf(Fs1) || std::isinf(Fs2) ||
820 if (signbit(Fs1) == signbit(Fs2)
821 && !std::isinf(Fs3)) {
822 Fd = numeric_limits<double>::infinity();
823 } else if (signbit(Fs1) != signbit(Fs2)
824 && !std::isinf(Fs3)) {
825 Fd = -numeric_limits<double>::infinity();
834 0x11: decode FUNCT2 {
837 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
838 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
839 float fs3 = reinterpret_cast<float&>(temp = Fs3_bits);
842 if (std::isnan(fs1) || std::isnan(fs2) ||
844 if (issignalingnan(fs1) || issignalingnan(fs2)
845 || issignalingnan(fs3)) {
846 FFLAGS |= FloatInvalid;
848 fd = numeric_limits<float>::quiet_NaN();
849 } else if (std::isinf(fs1) || std::isinf(fs2) ||
851 if (signbit(fs1) == signbit(fs2)
852 && !std::isinf(fs3)) {
853 fd = numeric_limits<float>::infinity();
854 } else if (signbit(fs1) != signbit(fs2)
855 && !std::isinf(fs3)) {
856 fd = -numeric_limits<float>::infinity();
857 } else { // Fs3_sf is infinity
863 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
866 if (std::isnan(Fs1) || std::isnan(Fs2) ||
868 if (issignalingnan(Fs1) || issignalingnan(Fs2)
869 || issignalingnan(Fs3)) {
870 FFLAGS |= FloatInvalid;
872 Fd = numeric_limits<double>::quiet_NaN();
873 } else if (std::isinf(Fs1) || std::isinf(Fs2) ||
875 if (signbit(Fs1) == signbit(Fs2)
876 && !std::isinf(Fs3)) {
877 Fd = numeric_limits<double>::infinity();
878 } else if (signbit(Fs1) != signbit(Fs2)
879 && !std::isinf(Fs3)) {
880 Fd = -numeric_limits<double>::infinity();
889 0x12: decode FUNCT2 {
892 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
893 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
894 float fs3 = reinterpret_cast<float&>(temp = Fs3_bits);
897 if (std::isnan(fs1) || std::isnan(fs2) ||
899 if (issignalingnan(fs1) || issignalingnan(fs2)
900 || issignalingnan(fs3)) {
901 FFLAGS |= FloatInvalid;
903 fd = numeric_limits<float>::quiet_NaN();
904 } else if (std::isinf(fs1) || std::isinf(fs2) ||
906 if (signbit(fs1) == signbit(fs2)
907 && !std::isinf(fs3)) {
908 fd = -numeric_limits<float>::infinity();
909 } else if (signbit(fs1) != signbit(fs2)
910 && !std::isinf(fs3)) {
911 fd = numeric_limits<float>::infinity();
912 } else { // Fs3_sf is infinity
916 fd = -(fs1*fs2 - fs3);
918 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
921 if (std::isnan(Fs1) || std::isnan(Fs2) ||
923 if (issignalingnan(Fs1) || issignalingnan(Fs2)
924 || issignalingnan(Fs3)) {
925 FFLAGS |= FloatInvalid;
927 Fd = numeric_limits<double>::quiet_NaN();
928 } else if (std::isinf(Fs1) || std::isinf(Fs2)
929 || std::isinf(Fs3)) {
930 if (signbit(Fs1) == signbit(Fs2)
931 && !std::isinf(Fs3)) {
932 Fd = -numeric_limits<double>::infinity();
933 } else if (signbit(Fs1) != signbit(Fs2)
934 && !std::isinf(Fs3)) {
935 Fd = numeric_limits<double>::infinity();
940 Fd = -(Fs1*Fs2 - Fs3);
944 0x13: decode FUNCT2 {
947 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
948 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
949 float fs3 = reinterpret_cast<float&>(temp = Fs3_bits);
952 if (std::isnan(fs1) || std::isnan(fs2) ||
954 if (issignalingnan(fs1) || issignalingnan(fs2)
955 || issignalingnan(fs3)) {
956 FFLAGS |= FloatInvalid;
958 fd = numeric_limits<float>::quiet_NaN();
959 } else if (std::isinf(fs1) || std::isinf(fs2) ||
961 if (signbit(fs1) == signbit(fs2)
962 && !std::isinf(fs3)) {
963 fd = -numeric_limits<float>::infinity();
964 } else if (signbit(fs1) != signbit(fs2)
965 && !std::isinf(fs3)) {
966 fd = numeric_limits<float>::infinity();
967 } else { // Fs3_sf is infinity
971 fd = -(fs1*fs2 + fs3);
973 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
976 if (std::isnan(Fs1) || std::isnan(Fs2) ||
978 if (issignalingnan(Fs1) || issignalingnan(Fs2)
979 || issignalingnan(Fs3)) {
980 FFLAGS |= FloatInvalid;
982 Fd = numeric_limits<double>::quiet_NaN();
983 } else if (std::isinf(Fs1) || std::isinf(Fs2) ||
985 if (signbit(Fs1) == signbit(Fs2)
986 && !std::isinf(Fs3)) {
987 Fd = -numeric_limits<double>::infinity();
988 } else if (signbit(Fs1) != signbit(Fs2)
989 && !std::isinf(Fs3)) {
990 Fd = numeric_limits<double>::infinity();
995 Fd = -(Fs1*Fs2 + Fs3);
999 0x14: decode FUNCT7 {
1002 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1003 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1006 if (std::isnan(fs1) || std::isnan(fs2)) {
1007 if (issignalingnan(fs1) || issignalingnan(fs2)) {
1008 FFLAGS |= FloatInvalid;
1010 fd = numeric_limits<float>::quiet_NaN();
1014 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1017 if (std::isnan(Fs1) || std::isnan(Fs2)) {
1018 if (issignalingnan(Fs1) || issignalingnan(Fs2)) {
1019 FFLAGS |= FloatInvalid;
1021 Fd = numeric_limits<double>::quiet_NaN();
1028 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1029 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1032 if (std::isnan(fs1) || std::isnan(fs2)) {
1033 if (issignalingnan(fs1) || issignalingnan(fs2)) {
1034 FFLAGS |= FloatInvalid;
1036 fd = numeric_limits<float>::quiet_NaN();
1040 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1043 if (std::isnan(Fs1) || std::isnan(Fs2)) {
1044 if (issignalingnan(Fs1) || issignalingnan(Fs2)) {
1045 FFLAGS |= FloatInvalid;
1047 Fd = numeric_limits<double>::quiet_NaN();
1054 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1055 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1058 if (std::isnan(fs1) || std::isnan(fs2)) {
1059 if (issignalingnan(fs1) || issignalingnan(fs2)) {
1060 FFLAGS |= FloatInvalid;
1062 fd = numeric_limits<float>::quiet_NaN();
1066 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1069 if (std::isnan(Fs1) || std::isnan(Fs2)) {
1070 if (issignalingnan(Fs1) || issignalingnan(Fs2)) {
1071 FFLAGS |= FloatInvalid;
1073 Fd = numeric_limits<double>::quiet_NaN();
1080 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1081 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1084 if (std::isnan(fs1) || std::isnan(fs2)) {
1085 if (issignalingnan(fs1) || issignalingnan(fs2)) {
1086 FFLAGS |= FloatInvalid;
1088 fd = numeric_limits<float>::quiet_NaN();
1092 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1095 if (std::isnan(Fs1) || std::isnan(Fs2)) {
1096 if (issignalingnan(Fs1) || issignalingnan(Fs2)) {
1097 FFLAGS |= FloatInvalid;
1099 Fd = numeric_limits<double>::quiet_NaN();
1104 0x10: decode ROUND_MODE {
1107 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1108 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1111 if (issignalingnan(fs1)) {
1112 fd = numeric_limits<float>::signaling_NaN();
1113 feclearexcept(FE_INVALID);
1115 fd = copysign(fs1, fs2);
1117 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1121 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1122 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1125 if (issignalingnan(fs1)) {
1126 fd = numeric_limits<float>::signaling_NaN();
1127 feclearexcept(FE_INVALID);
1129 fd = copysign(fs1, -fs2);
1131 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1135 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1136 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1139 if (issignalingnan(fs1)) {
1140 fd = numeric_limits<float>::signaling_NaN();
1141 feclearexcept(FE_INVALID);
1143 fd = fs1*(signbit(fs2) ? -1.0 : 1.0);
1145 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1148 0x11: decode ROUND_MODE {
1150 if (issignalingnan(Fs1)) {
1151 Fd = numeric_limits<double>::signaling_NaN();
1152 feclearexcept(FE_INVALID);
1154 Fd = copysign(Fs1, Fs2);
1158 if (issignalingnan(Fs1)) {
1159 Fd = numeric_limits<double>::signaling_NaN();
1160 feclearexcept(FE_INVALID);
1162 Fd = copysign(Fs1, -Fs2);
1166 if (issignalingnan(Fs1)) {
1167 Fd = numeric_limits<double>::signaling_NaN();
1168 feclearexcept(FE_INVALID);
1170 Fd = Fs1*(signbit(Fs2) ? -1.0 : 1.0);
1174 0x14: decode ROUND_MODE {
1177 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1178 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1181 if (issignalingnan(fs2)) {
1183 FFLAGS |= FloatInvalid;
1184 } else if (issignalingnan(fs1)) {
1186 FFLAGS |= FloatInvalid;
1188 fd = fmin(fs1, fs2);
1190 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1194 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1195 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1198 if (issignalingnan(fs2)) {
1200 FFLAGS |= FloatInvalid;
1201 } else if (issignalingnan(fs1)) {
1203 FFLAGS |= FloatInvalid;
1205 fd = fmax(fs1, fs2);
1207 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1210 0x15: decode ROUND_MODE {
1212 if (issignalingnan(Fs2)) {
1214 FFLAGS |= FloatInvalid;
1215 } else if (issignalingnan(Fs1)) {
1217 FFLAGS |= FloatInvalid;
1219 Fd = fmin(Fs1, Fs2);
1223 if (issignalingnan(Fs2)) {
1225 FFLAGS |= FloatInvalid;
1226 } else if (issignalingnan(Fs1)) {
1228 FFLAGS |= FloatInvalid;
1230 Fd = fmax(Fs1, Fs2);
1235 assert(CONV_SGN == 1);
1237 if (issignalingnan(Fs1)) {
1238 fd = numeric_limits<float>::quiet_NaN();
1239 FFLAGS |= FloatInvalid;
1243 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1246 assert(CONV_SGN == 0);
1248 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1250 if (issignalingnan(fs1)) {
1251 Fd = numeric_limits<double>::quiet_NaN();
1252 FFLAGS |= FloatInvalid;
1260 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1263 if (issignalingnan(Fs1_sf)) {
1264 FFLAGS |= FloatInvalid;
1267 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1273 0x50: decode ROUND_MODE {
1276 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1277 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1279 if (std::isnan(fs1) || std::isnan(fs2)) {
1280 FFLAGS |= FloatInvalid;
1283 Rd = fs1 <= fs2 ? 1 : 0;
1288 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1289 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1291 if (std::isnan(fs1) || std::isnan(fs2)) {
1292 FFLAGS |= FloatInvalid;
1295 Rd = fs1 < fs2 ? 1 : 0;
1300 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1301 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1303 if (issignalingnan(fs1) || issignalingnan(fs2)) {
1304 FFLAGS |= FloatInvalid;
1306 Rd = fs1 == fs2 ? 1 : 0;
1309 0x51: decode ROUND_MODE {
1311 if (std::isnan(Fs1) || std::isnan(Fs2)) {
1312 FFLAGS |= FloatInvalid;
1315 Rd = Fs1 <= Fs2 ? 1 : 0;
1319 if (std::isnan(Fs1) || std::isnan(Fs2)) {
1320 FFLAGS |= FloatInvalid;
1323 Rd = Fs1 < Fs2 ? 1 : 0;
1327 if (issignalingnan(Fs1) || issignalingnan(Fs2)) {
1328 FFLAGS |= FloatInvalid;
1330 Rd = Fs1 == Fs2 ? 1 : 0;
1333 0x60: decode CONV_SGN {
1336 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1338 if (std::isnan(fs1)) {
1339 Rd_sd = numeric_limits<int32_t>::max();
1340 FFLAGS |= FloatInvalid;
1342 Rd_sd = (int32_t)fs1;
1343 if (fetestexcept(FE_INVALID)) {
1345 Rd_sd = numeric_limits<int32_t>::min();
1347 Rd_sd = numeric_limits<int32_t>::max();
1349 feclearexcept(FE_INEXACT);
1355 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1359 FFLAGS |= FloatInvalid;
1362 if (fetestexcept(FE_INVALID)) {
1363 Rd = numeric_limits<uint64_t>::max();
1364 feclearexcept(FE_INEXACT);
1370 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1372 if (std::isnan(fs1)) {
1373 Rd_sd = numeric_limits<int64_t>::max();
1374 FFLAGS |= FloatInvalid;
1376 Rd_sd = (int64_t)fs1;
1377 if (fetestexcept(FE_INVALID)) {
1379 Rd_sd = numeric_limits<int64_t>::min();
1381 Rd_sd = numeric_limits<int64_t>::max();
1383 feclearexcept(FE_INEXACT);
1389 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1393 FFLAGS |= FloatInvalid;
1396 if (fetestexcept(FE_INVALID)) {
1397 Rd = numeric_limits<uint64_t>::max();
1398 feclearexcept(FE_INEXACT);
1403 0x61: decode CONV_SGN {
1405 Rd_sd = (int32_t)Fs1;
1406 if (fetestexcept(FE_INVALID)) {
1408 Rd_sd = numeric_limits<int32_t>::min();
1410 Rd_sd = numeric_limits<int32_t>::max();
1412 feclearexcept(FE_INEXACT);
1418 FFLAGS |= FloatInvalid;
1421 if (fetestexcept(FE_INVALID)) {
1422 Rd = numeric_limits<uint64_t>::max();
1423 feclearexcept(FE_INEXACT);
1429 if (fetestexcept(FE_INVALID)) {
1431 Rd_sd = numeric_limits<int64_t>::min();
1433 Rd_sd = numeric_limits<int64_t>::max();
1435 feclearexcept(FE_INEXACT);
1441 FFLAGS |= FloatInvalid;
1444 if (fetestexcept(FE_INVALID)) {
1445 Rd = numeric_limits<uint64_t>::max();
1446 feclearexcept(FE_INEXACT);
1451 0x68: decode CONV_SGN {
1453 float temp = (float)Rs1_sw;
1454 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(temp);
1457 float temp = (float)Rs1_uw;
1458 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(temp);
1461 float temp = (float)Rs1_sd;
1462 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(temp);
1465 float temp = (float)Rs1;
1466 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(temp);
1469 0x69: decode CONV_SGN {
1471 Fd = (double)Rs1_sw;
1474 Fd = (double)Rs1_uw;
1477 Fd = (double)Rs1_sd;
1483 0x70: decode ROUND_MODE {
1485 Rd = (uint32_t)Fs1_bits;
1486 if ((Rd&0x80000000) != 0) {
1487 Rd |= (0xFFFFFFFFULL << 32);
1492 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1493 switch (fpclassify(fs1)) {
1502 if (issignalingnan(fs1)) {
1530 panic("Unknown classification for operand.");
1535 0x71: decode ROUND_MODE {
1540 switch (fpclassify(Fs1)) {
1549 if (issignalingnan(Fs1)) {
1577 panic("Unknown classification for operand.");
1583 Fd_bits = (uint64_t)Rs1_uw;
1591 0x18: decode FUNCT3 {
1599 }}, IsDirectControl, IsCondControl);
1606 }}, IsDirectControl, IsCondControl);
1608 if (Rs1_sd < Rs2_sd) {
1613 }}, IsDirectControl, IsCondControl);
1615 if (Rs1_sd >= Rs2_sd) {
1620 }}, IsDirectControl, IsCondControl);
1627 }}, IsDirectControl, IsCondControl);
1634 }}, IsDirectControl, IsCondControl);
1638 0x19: decode FUNCT3 {
1641 NPC = (imm + Rs1) & (~0x1);
1642 }}, IsIndirectControl, IsUncondControl, IsCall);
1648 }}, IsDirectControl, IsUncondControl, IsCall);
1650 0x1c: decode FUNCT3 {
1652 0x0: decode FUNCT12 {
1654 fault = make_shared<SyscallFault>();
1655 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall,
1658 fault = make_shared<BreakpointFault>();
1659 }}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
1661 fault = make_shared<UnimplementedFault>("eret");
1667 Rd = xc->readMiscReg(csr);
1668 xc->setMiscReg(csr, Rs1);
1669 }}, IsNonSpeculative, No_OpClass);
1671 Rd = xc->readMiscReg(csr);
1673 xc->setMiscReg(csr, Rd | Rs1);
1675 }}, IsNonSpeculative, No_OpClass);
1677 Rd = xc->readMiscReg(csr);
1679 xc->setMiscReg(csr, Rd & ~Rs1);
1681 }}, IsNonSpeculative, No_OpClass);
1683 Rd = xc->readMiscReg(csr);
1684 xc->setMiscReg(csr, uimm);
1685 }}, IsNonSpeculative, No_OpClass);
1687 Rd = xc->readMiscReg(csr);
1689 xc->setMiscReg(csr, Rd | uimm);
1691 }}, IsNonSpeculative, No_OpClass);
1693 Rd = xc->readMiscReg(csr);
1695 xc->setMiscReg(csr, Rd & ~uimm);
1697 }}, IsNonSpeculative, No_OpClass);