src/arch/riscv/isa/includes.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2015 RISC-V Foundation
   4 // Copyright (c) 2016 The University of Virginia
   5 // All rights reserved.
   6 //
   7 // Redistribution and use in source and binary forms, with or without
   8 // modification, are permitted provided that the following conditions are
   9 // met: redistributions of source code must retain the above copyright
  10 // notice, this list of conditions and the following disclaimer;
  11 // redistributions in binary form must reproduce the above copyright
  12 // notice, this list of conditions and the following disclaimer in the
  13 // documentation and/or other materials provided with the distribution;
  14 // neither the name of the copyright holders nor the names of its
  15 // contributors may be used to endorse or promote products derived from
  16 // this software without specific prior written permission.
  17 //
  18 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  24 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  26 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  28 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29 //
  30 // Authors: Maxwell Walter
  31 //          Alec Roelke
  32
  33 ////////////////////////////////////////////////////////////////////
  34 //
  35 // Output include file directives.
  36 //
  37
  38 output header {{
  39 #include <iomanip>
  40 #include <sstream>
  41 #include <string>
  42 #include <tuple>
  43 #include <vector>
  44
  45 #include "cpu/static_inst.hh"
  46 #include "mem/packet.hh"
  47 #include "mem/request.hh"
  48
  49 }};
  50
  51 output decoder {{
  52 #include <cfenv>
  53 #include <cmath>
  54 #include <limits>
  55 #include <string>
  56
  57 #include "arch/riscv/decoder.hh"
  58 #include "arch/riscv/faults.hh"
  59 #include "arch/riscv/tlb.hh"
  60 #include "base/cprintf.hh"
  61 #include "base/loader/symtab.hh"
  62 #include "cpu/thread_context.hh"
  63 #include "mem/packet.hh"
  64 #include "mem/request.hh"
  65 #include "sim/full_system.hh"
  66
  67 using namespace RiscvISA;
  68 using namespace std;
  69 }};
  70
  71 output exec {{
  72 #include <cfenv>
  73 #include <cmath>
  74 #include <string>
  75 #include <vector>
  76
  77 #include "arch/generic/memhelpers.hh"
  78 #include "arch/riscv/faults.hh"
  79 #include "arch/riscv/registers.hh"
  80 #include "arch/riscv/utility.hh"
  81 #include "base/condcodes.hh"
  82 #include "cpu/base.hh"
  83 #include "cpu/exetrace.hh"
  84 #include "mem/packet.hh"
  85 #include "mem/packet_access.hh"
  86 #include "mem/request.hh"
  87 #include "sim/eventq.hh"
  88 #include "sim/full_system.hh"
  89 #include "sim/sim_events.hh"
  90 #include "sim/sim_exit.hh"
  91 #include "sim/system.hh"
  92
  93 using namespace RiscvISA;
  94 using namespace std;
  95 }};