3 // Copyright (c) 2015 RISC-V Foundation
4 // Copyright (c) 2016 The University of Virginia
5 // All rights reserved.
7 // Redistribution and use in source and binary forms, with or without
8 // modification, are permitted provided that the following conditions are
9 // met: redistributions of source code must retain the above copyright
10 // notice, this list of conditions and the following disclaimer;
11 // redistributions in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the distribution;
14 // neither the name of the copyright holders nor the names of its
15 // contributors may be used to endorse or promote products derived from
16 // this software without specific prior written permission.
18 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 ////////////////////////////////////////////////////////////////////
32 // Output include file directives.
42 #include "arch/riscv/insts/amo.hh"
43 #include "arch/riscv/insts/compressed.hh"
44 #include "arch/riscv/insts/mem.hh"
45 #include "arch/riscv/insts/standard.hh"
46 #include "arch/riscv/insts/static_inst.hh"
47 #include "arch/riscv/insts/unknown.hh"
48 #include "cpu/static_inst.hh"
49 #include "mem/packet.hh"
50 #include "mem/request.hh"
60 #include "arch/riscv/decoder.hh"
61 #include "arch/riscv/faults.hh"
62 #include "arch/riscv/tlb.hh"
63 #include "base/cprintf.hh"
64 #include "base/loader/symtab.hh"
65 #include "cpu/thread_context.hh"
66 #include "mem/packet.hh"
67 #include "mem/request.hh"
68 #include "sim/full_system.hh"
70 using namespace RiscvISA;
80 #include "arch/generic/memhelpers.hh"
81 #include "arch/riscv/faults.hh"
82 #include "arch/riscv/registers.hh"
83 #include "arch/riscv/utility.hh"
84 #include "base/condcodes.hh"
85 #include "cpu/base.hh"
86 #include "cpu/exetrace.hh"
87 #include "debug/RiscvMisc.hh"
88 #include "mem/packet.hh"
89 #include "mem/packet_access.hh"
90 #include "mem/request.hh"
91 #include "sim/eventq.hh"
92 #include "sim/full_system.hh"
93 #include "sim/sim_events.hh"
94 #include "sim/sim_exit.hh"
95 #include "sim/system.hh"
97 using namespace RiscvISA;