src/arch/riscv/isa/operands.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2015 RISC-V Foundation
   4 // Copyright (c) 2016 The University of Virginia
   5 // All rights reserved.
   6 //
   7 // Redistribution and use in source and binary forms, with or without
   8 // modification, are permitted provided that the following conditions are
   9 // met: redistributions of source code must retain the above copyright
  10 // notice, this list of conditions and the following disclaimer;
  11 // redistributions in binary form must reproduce the above copyright
  12 // notice, this list of conditions and the following disclaimer in the
  13 // documentation and/or other materials provided with the distribution;
  14 // neither the name of the copyright holders nor the names of its
  15 // contributors may be used to endorse or promote products derived from
  16 // this software without specific prior written permission.
  17 //
  18 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  21 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  24 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  28 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29 //
  30 // Authors: Maxwell Walter
  31 //          Alec Roelke
  32
  33 def operand_types {{
  34     'sb' : 'int8_t',
  35     'ub' : 'uint8_t',
  36     'sh' : 'int16_t',
  37     'uh' : 'uint16_t',
  38     'sw' : 'int32_t',
  39     'uw' : 'uint32_t',
  40     'sd' : 'int64_t',
  41     'ud' : 'uint64_t',
  42     'sf' : 'float',
  43     'df' : 'double'
  44 }};
  45
  46 def operands {{
  47 #General Purpose Integer Reg Operands
  48     'Rd': ('IntReg', 'ud', 'RD', 'IsInteger', 1),
  49     'Rs1': ('IntReg', 'ud', 'RS1', 'IsInteger', 2),
  50     'Rs2': ('IntReg', 'ud', 'RS2', 'IsInteger', 3),
  51     'Rt': ('IntReg', 'ud', 'AMOTempReg', 'IsInteger', 4),
  52     'Rc1': ('IntReg', 'ud', 'RC1', 'IsInteger', 2),
  53     'Rc2': ('IntReg', 'ud', 'RC2', 'IsInteger', 3),
  54     'Rp1': ('IntReg', 'ud', 'RP1 + 8', 'IsInteger', 2),
  55     'Rp2': ('IntReg', 'ud', 'RP2 + 8', 'IsInteger', 3),
  56     'ra': ('IntReg', 'ud', 'ReturnAddrReg', 'IsInteger', 1),
  57     'sp': ('IntReg', 'ud', 'StackPointerReg', 'IsInteger', 2),
  58
  59     'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1),
  60     'Fd_bits': ('FloatReg', 'ud', 'FD', 'IsFloating', 1),
  61     'Fs1': ('FloatReg', 'df', 'FS1', 'IsFloating', 2),
  62     'Fs1_bits': ('FloatReg', 'ud', 'FS1', 'IsFloating', 2),
  63     'Fs2': ('FloatReg', 'df', 'FS2', 'IsFloating', 3),
  64     'Fs2_bits': ('FloatReg', 'ud', 'FS2', 'IsFloating', 3),
  65     'Fs3': ('FloatReg', 'df', 'FS3', 'IsFloating', 4),
  66     'Fs3_bits': ('FloatReg', 'ud', 'FS3', 'IsFloating', 4),
  67     'Fc1': ('FloatReg', 'df', 'FC1', 'IsFloating', 1),
  68     'Fc1_bits': ('FloatReg', 'ud', 'FC1', 'IsFloating', 1),
  69     'Fc2': ('FloatReg', 'df', 'FC2', 'IsFloatReg', 2),
  70     'Fc2_bits': ('FloatReg', 'ud', 'FC2', 'IsFloating', 2),
  71     'Fp2': ('FloatReg', 'df', 'FP2 + 8', 'IsFloating', 2),
  72     'Fp2_bits': ('FloatReg', 'ud', 'FP2 + 8', 'IsFloating', 2),
  73
  74 #Memory Operand
  75     'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 5),
  76
  77 #Program Counter Operands
  78     'PC': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 7),
  79     'NPC': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 8),
  80 }};