2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * Copyright (c) 2020 Barkhausen Institut
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
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15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 #include "arch/riscv/isa.hh"
37 #include "arch/riscv/interrupts.hh"
38 #include "arch/riscv/pagetable.hh"
39 #include "arch/riscv/registers.hh"
40 #include "base/bitfield.hh"
41 #include "cpu/base.hh"
42 #include "debug/RiscvMisc.hh"
43 #include "params/RiscvISA.hh"
44 #include "sim/core.hh"
45 #include "sim/pseudo_inst.hh"
50 const std::array
<const char *, NumMiscRegs
> MiscRegNames
= {{
51 [MISCREG_PRV
] = "PRV",
52 [MISCREG_ISA
] = "ISA",
53 [MISCREG_VENDORID
] = "VENDORID",
54 [MISCREG_ARCHID
] = "ARCHID",
55 [MISCREG_IMPID
] = "IMPID",
56 [MISCREG_HARTID
] = "HARTID",
57 [MISCREG_STATUS
] = "STATUS",
60 [MISCREG_CYCLE
] = "CYCLE",
61 [MISCREG_TIME
] = "TIME",
62 [MISCREG_INSTRET
] = "INSTRET",
63 [MISCREG_HPMCOUNTER03
] = "HPMCOUNTER03",
64 [MISCREG_HPMCOUNTER04
] = "HPMCOUNTER04",
65 [MISCREG_HPMCOUNTER05
] = "HPMCOUNTER05",
66 [MISCREG_HPMCOUNTER06
] = "HPMCOUNTER06",
67 [MISCREG_HPMCOUNTER07
] = "HPMCOUNTER07",
68 [MISCREG_HPMCOUNTER08
] = "HPMCOUNTER08",
69 [MISCREG_HPMCOUNTER09
] = "HPMCOUNTER09",
70 [MISCREG_HPMCOUNTER10
] = "HPMCOUNTER10",
71 [MISCREG_HPMCOUNTER11
] = "HPMCOUNTER11",
72 [MISCREG_HPMCOUNTER12
] = "HPMCOUNTER12",
73 [MISCREG_HPMCOUNTER13
] = "HPMCOUNTER13",
74 [MISCREG_HPMCOUNTER14
] = "HPMCOUNTER14",
75 [MISCREG_HPMCOUNTER15
] = "HPMCOUNTER15",
76 [MISCREG_HPMCOUNTER16
] = "HPMCOUNTER16",
77 [MISCREG_HPMCOUNTER17
] = "HPMCOUNTER17",
78 [MISCREG_HPMCOUNTER18
] = "HPMCOUNTER18",
79 [MISCREG_HPMCOUNTER19
] = "HPMCOUNTER19",
80 [MISCREG_HPMCOUNTER20
] = "HPMCOUNTER20",
81 [MISCREG_HPMCOUNTER21
] = "HPMCOUNTER21",
82 [MISCREG_HPMCOUNTER22
] = "HPMCOUNTER22",
83 [MISCREG_HPMCOUNTER23
] = "HPMCOUNTER23",
84 [MISCREG_HPMCOUNTER24
] = "HPMCOUNTER24",
85 [MISCREG_HPMCOUNTER25
] = "HPMCOUNTER25",
86 [MISCREG_HPMCOUNTER26
] = "HPMCOUNTER26",
87 [MISCREG_HPMCOUNTER27
] = "HPMCOUNTER27",
88 [MISCREG_HPMCOUNTER28
] = "HPMCOUNTER28",
89 [MISCREG_HPMCOUNTER29
] = "HPMCOUNTER29",
90 [MISCREG_HPMCOUNTER30
] = "HPMCOUNTER30",
91 [MISCREG_HPMCOUNTER31
] = "HPMCOUNTER31",
92 [MISCREG_HPMEVENT03
] = "HPMEVENT03",
93 [MISCREG_HPMEVENT04
] = "HPMEVENT04",
94 [MISCREG_HPMEVENT05
] = "HPMEVENT05",
95 [MISCREG_HPMEVENT06
] = "HPMEVENT06",
96 [MISCREG_HPMEVENT07
] = "HPMEVENT07",
97 [MISCREG_HPMEVENT08
] = "HPMEVENT08",
98 [MISCREG_HPMEVENT09
] = "HPMEVENT09",
99 [MISCREG_HPMEVENT10
] = "HPMEVENT10",
100 [MISCREG_HPMEVENT11
] = "HPMEVENT11",
101 [MISCREG_HPMEVENT12
] = "HPMEVENT12",
102 [MISCREG_HPMEVENT13
] = "HPMEVENT13",
103 [MISCREG_HPMEVENT14
] = "HPMEVENT14",
104 [MISCREG_HPMEVENT15
] = "HPMEVENT15",
105 [MISCREG_HPMEVENT16
] = "HPMEVENT16",
106 [MISCREG_HPMEVENT17
] = "HPMEVENT17",
107 [MISCREG_HPMEVENT18
] = "HPMEVENT18",
108 [MISCREG_HPMEVENT19
] = "HPMEVENT19",
109 [MISCREG_HPMEVENT20
] = "HPMEVENT20",
110 [MISCREG_HPMEVENT21
] = "HPMEVENT21",
111 [MISCREG_HPMEVENT22
] = "HPMEVENT22",
112 [MISCREG_HPMEVENT23
] = "HPMEVENT23",
113 [MISCREG_HPMEVENT24
] = "HPMEVENT24",
114 [MISCREG_HPMEVENT25
] = "HPMEVENT25",
115 [MISCREG_HPMEVENT26
] = "HPMEVENT26",
116 [MISCREG_HPMEVENT27
] = "HPMEVENT27",
117 [MISCREG_HPMEVENT28
] = "HPMEVENT28",
118 [MISCREG_HPMEVENT29
] = "HPMEVENT29",
119 [MISCREG_HPMEVENT30
] = "HPMEVENT30",
120 [MISCREG_HPMEVENT31
] = "HPMEVENT31",
121 [MISCREG_TSELECT
] = "TSELECT",
122 [MISCREG_TDATA1
] = "TDATA1",
123 [MISCREG_TDATA2
] = "TDATA2",
124 [MISCREG_TDATA3
] = "TDATA3",
125 [MISCREG_DCSR
] = "DCSR",
126 [MISCREG_DPC
] = "DPC",
127 [MISCREG_DSCRATCH
] = "DSCRATCH",
129 [MISCREG_MEDELEG
] = "MEDELEG",
130 [MISCREG_MIDELEG
] = "MIDELEG",
131 [MISCREG_MTVEC
] = "MTVEC",
132 [MISCREG_MCOUNTEREN
] = "MCOUNTEREN",
133 [MISCREG_MSCRATCH
] = "MSCRATCH",
134 [MISCREG_MEPC
] = "MEPC",
135 [MISCREG_MCAUSE
] = "MCAUSE",
136 [MISCREG_MTVAL
] = "MTVAL",
137 [MISCREG_PMPCFG0
] = "PMPCFG0",
139 [MISCREG_PMPCFG2
] = "PMPCFG2",
141 [MISCREG_PMPADDR00
] = "PMPADDR00",
142 [MISCREG_PMPADDR01
] = "PMPADDR01",
143 [MISCREG_PMPADDR02
] = "PMPADDR02",
144 [MISCREG_PMPADDR03
] = "PMPADDR03",
145 [MISCREG_PMPADDR04
] = "PMPADDR04",
146 [MISCREG_PMPADDR05
] = "PMPADDR05",
147 [MISCREG_PMPADDR06
] = "PMPADDR06",
148 [MISCREG_PMPADDR07
] = "PMPADDR07",
149 [MISCREG_PMPADDR08
] = "PMPADDR08",
150 [MISCREG_PMPADDR09
] = "PMPADDR09",
151 [MISCREG_PMPADDR10
] = "PMPADDR10",
152 [MISCREG_PMPADDR11
] = "PMPADDR11",
153 [MISCREG_PMPADDR12
] = "PMPADDR12",
154 [MISCREG_PMPADDR13
] = "PMPADDR13",
155 [MISCREG_PMPADDR14
] = "PMPADDR14",
156 [MISCREG_PMPADDR15
] = "PMPADDR15",
158 [MISCREG_SEDELEG
] = "SEDELEG",
159 [MISCREG_SIDELEG
] = "SIDELEG",
160 [MISCREG_STVEC
] = "STVEC",
161 [MISCREG_SCOUNTEREN
] = "SCOUNTEREN",
162 [MISCREG_SSCRATCH
] = "SSCRATCH",
163 [MISCREG_SEPC
] = "SEPC",
164 [MISCREG_SCAUSE
] = "SCAUSE",
165 [MISCREG_STVAL
] = "STVAL",
166 [MISCREG_SATP
] = "SATP",
168 [MISCREG_UTVEC
] = "UTVEC",
169 [MISCREG_USCRATCH
] = "USCRATCH",
170 [MISCREG_UEPC
] = "UEPC",
171 [MISCREG_UCAUSE
] = "UCAUSE",
172 [MISCREG_UTVAL
] = "UTVAL",
173 [MISCREG_FFLAGS
] = "FFLAGS",
174 [MISCREG_FRM
] = "FRM",
177 ISA::ISA(Params
*p
) : BaseISA(p
)
179 miscRegFile
.resize(NumMiscRegs
);
183 const RiscvISAParams
*
186 return dynamic_cast<const Params
*>(_params
);
191 std::fill(miscRegFile
.begin(), miscRegFile
.end(), 0);
193 miscRegFile
[MISCREG_PRV
] = PRV_M
;
194 miscRegFile
[MISCREG_ISA
] = (2ULL << MXL_OFFSET
) | 0x14112D;
195 miscRegFile
[MISCREG_VENDORID
] = 0;
196 miscRegFile
[MISCREG_ARCHID
] = 0;
197 miscRegFile
[MISCREG_IMPID
] = 0;
198 miscRegFile
[MISCREG_STATUS
] = (2ULL << UXL_OFFSET
) | (2ULL << SXL_OFFSET
) |
200 miscRegFile
[MISCREG_MCOUNTEREN
] = 0x7;
201 miscRegFile
[MISCREG_SCOUNTEREN
] = 0x7;
205 ISA::hpmCounterEnabled(int misc_reg
) const
207 int hpmcounter
= misc_reg
- MISCREG_CYCLE
;
208 if (hpmcounter
< 0 || hpmcounter
> 31)
209 panic("Illegal HPM counter %d\n", hpmcounter
);
211 switch (readMiscRegNoEffect(MISCREG_PRV
)) {
215 counteren
= MISCREG_MCOUNTEREN
;
218 counteren
= MISCREG_SCOUNTEREN
;
221 panic("Unknown privilege level %d\n", miscRegFile
[MISCREG_PRV
]);
224 return (miscRegFile
[counteren
] & (1ULL << (hpmcounter
))) > 0;
228 ISA::readMiscRegNoEffect(int misc_reg
) const
230 if (misc_reg
> NumMiscRegs
|| misc_reg
< 0) {
232 panic("Illegal CSR index %#x\n", misc_reg
);
235 DPRINTF(RiscvMisc
, "Reading MiscReg %s (%d): %#x.\n",
236 MiscRegNames
[misc_reg
], misc_reg
, miscRegFile
[misc_reg
]);
237 return miscRegFile
[misc_reg
];
241 ISA::readMiscReg(int misc_reg
, ThreadContext
*tc
)
245 return tc
->contextId();
247 if (hpmCounterEnabled(MISCREG_CYCLE
)) {
248 DPRINTF(RiscvMisc
, "Cycle counter at: %llu.\n",
249 tc
->getCpuPtr()->curCycle());
250 return tc
->getCpuPtr()->curCycle();
252 warn("Cycle counter disabled.\n");
256 if (hpmCounterEnabled(MISCREG_TIME
)) {
257 DPRINTF(RiscvMisc
, "Wall-clock counter at: %llu.\n",
259 return std::time(nullptr);
261 warn("Wall clock disabled.\n");
264 case MISCREG_INSTRET
:
265 if (hpmCounterEnabled(MISCREG_INSTRET
)) {
266 DPRINTF(RiscvMisc
, "Instruction counter at: %llu.\n",
267 tc
->getCpuPtr()->totalInsts());
268 return tc
->getCpuPtr()->totalInsts();
270 warn("Instruction counter disabled.\n");
275 auto ic
= dynamic_cast<RiscvISA::Interrupts
*>(
276 tc
->getCpuPtr()->getInterruptController(tc
->threadId()));
281 auto ic
= dynamic_cast<RiscvISA::Interrupts
*>(
282 tc
->getCpuPtr()->getInterruptController(tc
->threadId()));
286 // Try reading HPM counters
287 // As a placeholder, all HPM counters are just cycle counters
288 if (misc_reg
>= MISCREG_HPMCOUNTER03
&&
289 misc_reg
<= MISCREG_HPMCOUNTER31
) {
290 if (hpmCounterEnabled(misc_reg
)) {
291 DPRINTF(RiscvMisc
, "HPM counter %d: %llu.\n",
292 misc_reg
- MISCREG_CYCLE
, tc
->getCpuPtr()->curCycle());
293 return tc
->getCpuPtr()->curCycle();
295 warn("HPM counter %d disabled.\n", misc_reg
- MISCREG_CYCLE
);
299 return readMiscRegNoEffect(misc_reg
);
304 ISA::setMiscRegNoEffect(int misc_reg
, RegVal val
)
306 if (misc_reg
> NumMiscRegs
|| misc_reg
< 0) {
308 panic("Illegal CSR index %#x\n", misc_reg
);
310 DPRINTF(RiscvMisc
, "Setting MiscReg %s (%d) to %#x.\n",
311 MiscRegNames
[misc_reg
], misc_reg
, val
);
312 miscRegFile
[misc_reg
] = val
;
316 ISA::setMiscReg(int misc_reg
, RegVal val
, ThreadContext
*tc
)
318 if (misc_reg
>= MISCREG_CYCLE
&& misc_reg
<= MISCREG_HPMCOUNTER31
) {
319 // Ignore writes to HPM counters for now
320 warn("Ignoring write to %s.\n", CSRData
.at(misc_reg
).name
);
325 auto ic
= dynamic_cast<RiscvISA::Interrupts
*>(
326 tc
->getCpuPtr()->getInterruptController(tc
->threadId()));
332 auto ic
= dynamic_cast<RiscvISA::Interrupts
*>(
333 tc
->getCpuPtr()->getInterruptController(tc
->threadId()));
339 // we only support bare and Sv39 mode; setting a different mode
340 // shall have no effect (see 4.1.12 in priv ISA manual)
341 SATP cur_val
= readMiscRegNoEffect(misc_reg
);
343 if (new_val
.mode
!= AddrXlateMode::BARE
&&
344 new_val
.mode
!= AddrXlateMode::SV39
)
345 new_val
.mode
= cur_val
.mode
;
346 setMiscRegNoEffect(misc_reg
, new_val
);
350 setMiscRegNoEffect(misc_reg
, val
);
358 RiscvISAParams::create()
360 return new RiscvISA::ISA(this);