src/arch/riscv/isa_traits.hh

   1 /*
   2  * Copyright (c) 2013 ARM Limited
   3  * Copyright (c) 2014-2015 Sven Karlsson
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2016 The University of Virginia
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Andreas Hansson
  42  *          Sven Karlsson
  43  *          Alec Roelke
  44  */
  45
  46 #ifndef __ARCH_RISCV_ISA_TRAITS_HH__
  47 #define __ARCH_RISCV_ISA_TRAITS_HH__
  48
  49 #include "arch/riscv/types.hh"
  50 #include "base/types.hh"
  51 #include "cpu/static_inst_fwd.hh"
  52
  53 namespace LittleEndianGuest {}
  54
  55 namespace RiscvISA
  56 {
  57
  58 using namespace LittleEndianGuest;
  59
  60 // Riscv does NOT have a delay slot
  61 #define ISA_HAS_DELAY_SLOT 0
  62
  63 const Addr PageShift = 12;
  64 const Addr PageBytes = ULL(1) << PageShift;
  65
  66 // Memory accesses can not be unaligned
  67 const bool HasUnalignedMemAcc = false;
  68
  69 const bool CurThreadInfoImplemented = false;
  70 const int CurThreadInfoReg = -1;
  71
  72 }
  73
  74 #endif //__ARCH_RISCV_ISA_TRAITS_HH__