src/arch/riscv/locked_mem.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * Copyright (c) 2007-2008 The Florida State University
   4  * Copyright (c) 2009 The University of Edinburgh
   5  * Copyright (c) 2012 ARM Limited
   6  * Copyright (c) 2014-2015 Sven Karlsson
   7  * All rights reserved.
   8  *
   9  * The license below extends only to copyright in the software and shall
  10  * not be construed as granting a license to any other intellectual
  11  * property including but not limited to intellectual property relating
  12  * to a hardware implementation of the functionality of the software
  13  * licensed hereunder.  You may use the software subject to the license
  14  * terms below provided that you ensure that this notice is replicated
  15  * unmodified and in its entirety in all distributions of the software,
  16  * modified or unmodified, in source code or in binary form.
  17  *
  18  * Copyright (c) 2006-2007 The Regents of The University of Michigan
  19  * Copyright (c) 2016 The University of Virginia
  20  * All rights reserved.
  21  *
  22  * Redistribution and use in source and binary forms, with or without
  23  * modification, are permitted provided that the following conditions are
  24  * met: redistributions of source code must retain the above copyright
  25  * notice, this list of conditions and the following disclaimer;
  26  * redistributions in binary form must reproduce the above copyright
  27  * notice, this list of conditions and the following disclaimer in the
  28  * documentation and/or other materials provided with the distribution;
  29  * neither the name of the copyright holders nor the names of its
  30  * contributors may be used to endorse or promote products derived from
  31  * this software without specific prior written permission.
  32  *
  33  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  34  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  35  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  36  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  37  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  38  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  39  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  40  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  41  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  42  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  43  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  44  */
  45
  46 #ifndef __ARCH_RISCV_LOCKED_MEM_HH__
  47 #define __ARCH_RISCV_LOCKED_MEM_HH__
  48
  49 #include <stack>
  50 #include <unordered_map>
  51
  52 #include "arch/registers.hh"
  53 #include "base/logging.hh"
  54 #include "base/trace.hh"
  55 #include "cpu/base.hh"
  56 #include "debug/LLSC.hh"
  57 #include "mem/packet.hh"
  58 #include "mem/request.hh"
  59
  60 /*
  61  * ISA-specific helper functions for locked memory accesses.
  62  */
  63 namespace RiscvISA
  64 {
  65
  66 const int WARN_FAILURE = 10000;
  67
  68 // RISC-V allows multiple locks per hart, but each SC has to unlock the most
  69 // recent one, so we use a stack here.
  70 extern std::unordered_map<int, std::stack<Addr>> locked_addrs;
  71
  72 template <class XC> inline void
  73 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
  74 {
  75     std::stack<Addr>& locked_addr_stack = locked_addrs[xc->contextId()];
  76
  77     if (locked_addr_stack.empty())
  78         return;
  79     Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
  80     DPRINTF(LLSC, "Locked snoop on address %x.\n", snoop_addr);
  81     if ((locked_addr_stack.top() & cacheBlockMask) == snoop_addr)
  82         locked_addr_stack.pop();
  83 }
  84
  85
  86 template <class XC> inline void
  87 handleLockedRead(XC *xc, const RequestPtr &req)
  88 {
  89     std::stack<Addr>& locked_addr_stack = locked_addrs[xc->contextId()];
  90
  91     locked_addr_stack.push(req->getPaddr() & ~0xF);
  92     DPRINTF(LLSC, "[cid:%d]: Reserved address %x.\n",
  93             req->contextId(), req->getPaddr() & ~0xF);
  94 }
  95
  96 template <class XC> inline void
  97 handleLockedSnoopHit(XC *xc)
  98 {}
  99
 100 template <class XC> inline bool
 101 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
 102 {
 103     std::stack<Addr>& locked_addr_stack = locked_addrs[xc->contextId()];
 104
 105     // Normally RISC-V uses zero to indicate success and nonzero to indicate
 106     // failure (right now only 1 is reserved), but in gem5 zero indicates
 107     // failure and one indicates success, so here we conform to that (it should
 108     // be switched in the instruction's implementation)
 109
 110     DPRINTF(LLSC, "[cid:%d]: locked_addrs empty? %s.\n", req->contextId(),
 111             locked_addr_stack.empty() ? "yes" : "no");
 112     if (!locked_addr_stack.empty()) {
 113         DPRINTF(LLSC, "[cid:%d]: addr = %x.\n", req->contextId(),
 114                 req->getPaddr() & ~0xF);
 115         DPRINTF(LLSC, "[cid:%d]: last locked addr = %x.\n", req->contextId(),
 116                 locked_addr_stack.top());
 117     }
 118     if (locked_addr_stack.empty()
 119             || locked_addr_stack.top() != ((req->getPaddr() & ~0xF))) {
 120         req->setExtraData(0);
 121         int stCondFailures = xc->readStCondFailures();
 122         xc->setStCondFailures(++stCondFailures);
 123         if (stCondFailures % WARN_FAILURE == 0) {
 124             warn("%i: context %d: %d consecutive SC failures.\n",
 125                     curTick(), xc->contextId(), stCondFailures);
 126         }
 127         return false;
 128     }
 129     if (req->isUncacheable()) {
 130         req->setExtraData(2);
 131     }
 132     return true;
 133 }
 134
 135 template <class XC>
 136 inline void
 137 globalClearExclusive(XC *xc)
 138 {
 139     xc->getCpuPtr()->wakeup(xc->threadId());
 140 }
 141
 142 } // namespace RiscvISA
 143
 144 #endif // __ARCH_RISCV_LOCKED_MEM_HH__