src/arch/riscv/locked_mem.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * Copyright (c) 2007-2008 The Florida State University
   4  * Copyright (c) 2009 The University of Edinburgh
   5  * Copyright (c) 2012 ARM Limited
   6  * Copyright (c) 2014-2015 Sven Karlsson
   7  * All rights reserved.
   8  *
   9  * The license below extends only to copyright in the software and shall
  10  * not be construed as granting a license to any other intellectual
  11  * property including but not limited to intellectual property relating
  12  * to a hardware implementation of the functionality of the software
  13  * licensed hereunder.  You may use the software subject to the license
  14  * terms below provided that you ensure that this notice is replicated
  15  * unmodified and in its entirety in all distributions of the software,
  16  * modified or unmodified, in source code or in binary form.
  17  *
  18  * Copyright (c) 2006-2007 The Regents of The University of Michigan
  19  * Copyright (c) 2016 The University of Virginia
  20  * All rights reserved.
  21  *
  22  * Redistribution and use in source and binary forms, with or without
  23  * modification, are permitted provided that the following conditions are
  24  * met: redistributions of source code must retain the above copyright
  25  * notice, this list of conditions and the following disclaimer;
  26  * redistributions in binary form must reproduce the above copyright
  27  * notice, this list of conditions and the following disclaimer in the
  28  * documentation and/or other materials provided with the distribution;
  29  * neither the name of the copyright holders nor the names of its
  30  * contributors may be used to endorse or promote products derived from
  31  * this software without specific prior written permission.
  32  *
  33  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  34  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  35  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  36  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  37  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  38  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  39  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  40  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  41  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  42  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  43  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  44  *
  45  * Authors: Steve Reinhardt
  46  *          Alec Roelke
  47  */
  48 #ifndef __ARCH_RISCV_LOCKED_MEM_HH__
  49 #define __ARCH_RISCV_LOCKED_MEM_HH__
  50
  51 #include <stack>
  52
  53 #include "arch/registers.hh"
  54 #include "base/misc.hh"
  55 #include "base/trace.hh"
  56 #include "debug/LLSC.hh"
  57 #include "mem/packet.hh"
  58 #include "mem/request.hh"
  59
  60 /*
  61  * ISA-specific helper functions for locked memory accesses.
  62  */
  63 namespace RiscvISA
  64 {
  65
  66 const int WARN_FAILURE = 10000;
  67
  68 // RISC-V allows multiple locks per hart, but each SC has to unlock the most
  69 // recent one, so we use a stack here.
  70 extern std::stack<Addr> locked_addrs;
  71
  72 template <class XC> inline void
  73 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
  74 {
  75     if (locked_addrs.empty())
  76         return;
  77     Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
  78     DPRINTF(LLSC, "Locked snoop on address %x.\n", snoop_addr);
  79     if ((locked_addrs.top() & cacheBlockMask) == snoop_addr)
  80         locked_addrs.pop();
  81 }
  82
  83
  84 template <class XC> inline void
  85 handleLockedRead(XC *xc, Request *req)
  86 {
  87     locked_addrs.push(req->getPaddr() & ~0xF);
  88     DPRINTF(LLSC, "[cid:%d]: Reserved address %x.\n",
  89             req->contextId(), req->getPaddr() & ~0xF);
  90 }
  91
  92 template <class XC> inline void
  93 handleLockedSnoopHit(XC *xc)
  94 {}
  95
  96 template <class XC> inline bool
  97 handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
  98 {
  99     // Normally RISC-V uses zero to indicate success and nonzero to indicate
 100     // failure (right now only 1 is reserved), but in gem5 zero indicates
 101     // failure and one indicates success, so here we conform to that (it should
 102     // be switched in the instruction's implementation)
 103
 104     DPRINTF(LLSC, "[cid:%d]: locked_addrs empty? %s.\n", req->contextId(),
 105             locked_addrs.empty() ? "yes" : "no");
 106     if (!locked_addrs.empty()) {
 107         DPRINTF(LLSC, "[cid:%d]: addr = %x.\n", req->contextId(),
 108                 req->getPaddr() & ~0xF);
 109         DPRINTF(LLSC, "[cid:%d]: last locked addr = %x.\n", req->contextId(),
 110                 locked_addrs.top());
 111     }
 112     if (locked_addrs.empty()
 113             || locked_addrs.top() != ((req->getPaddr() & ~0xF))) {
 114         req->setExtraData(0);
 115         int stCondFailures = xc->readStCondFailures();
 116         xc->setStCondFailures(++stCondFailures);
 117         if (stCondFailures % WARN_FAILURE == 0) {
 118             warn("%i: context %d: %d consecutive SC failures.\n",
 119                     curTick(), xc->contextId(), stCondFailures);
 120         }
 121         return false;
 122     }
 123     if (req->isUncacheable()) {
 124         req->setExtraData(2);
 125     }
 126     return true;
 127 }
 128
 129 } // namespace RiscvISA
 130
 131 #endif // __ARCH_RISCV_LOCKED_MEM_HH__