src/arch/riscv/pra_constants.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __ARCH_RISCV_PRA_CONSTANTS_HH__
  30 #define __ARCH_RISCV_PRA_CONSTANTS_HH__
  31
  32 #include "arch/riscv/types.hh"
  33 #include "base/bitunion.hh"
  34
  35 namespace RiscvISA
  36 {
  37
  38 BitUnion32(IndexReg)
  39     Bitfield<31> p;
  40     // Need to figure out how to put in the TLB specific bits here
  41     // For now, we assume that the entire length is used by the index
  42     // field In reality, Index_HI = N-1, where
  43     // N = Ceiling(log2(TLB Entries))
  44     Bitfield<30, 0> index;
  45 EndBitUnion(IndexReg)
  46
  47 BitUnion32(RandomReg)
  48     // This has a problem similar to the IndexReg index field. We'll keep
  49     // both consistent at 30 for now
  50     Bitfield<30, 0> random;
  51 EndBitUnion(RandomReg)
  52
  53 BitUnion64(EntryLoReg)
  54     Bitfield<63, 30> fill;
  55     Bitfield<29, 6>  pfn;   // Page frame number
  56     Bitfield<5,  3>  c;     // Coherency attribute
  57     Bitfield<2>      d;     // Dirty Bit
  58     Bitfield<1>      v;     // Valid Bit
  59     Bitfield<0>      g;     // Global Bit
  60 EndBitUnion(EntryLoReg)
  61
  62 BitUnion64(ContextReg)
  63     Bitfield<63, 23> pteBase;
  64     Bitfield<22, 4>  badVPN2;
  65     // Bits 3-0 are 0
  66 EndBitUnion(ContextReg)
  67
  68 BitUnion32(PageMaskReg)
  69     // Bits 31-29 are 0
  70     Bitfield<28, 13> mask;
  71     Bitfield<12, 11> maskx;
  72     // Bits 10-0 are zero
  73 EndBitUnion(PageMaskReg)
  74
  75 BitUnion32(PageGrainReg)
  76     Bitfield<31, 30> aseUp;
  77     Bitfield<29>     elpa;
  78     Bitfield<28>     esp;
  79     // Bits 27-13 are zeros
  80     Bitfield<12, 8>  aseDn;
  81     // Bits 7-0 are zeros
  82 EndBitUnion(PageGrainReg)
  83
  84 BitUnion32(WiredReg)
  85     // See note on Index register above
  86     Bitfield<30, 0> wired;
  87 EndBitUnion(WiredReg)
  88
  89 BitUnion32(HWREnaReg)
  90     Bitfield<31, 30> impl;
  91     Bitfield<3,  0>  mask;
  92 EndBitUnion(HWREnaReg)
  93
  94 BitUnion64(EntryHiReg)
  95     Bitfield<63, 62> r;
  96     Bitfield<61, 40> fill;
  97     Bitfield<39, 13> vpn2;
  98     Bitfield<12, 11> vpn2x;
  99     Bitfield<7,  0>  asid;
 100 EndBitUnion(EntryHiReg)
 101
 102 BitUnion32(StatusReg)
 103     SubBitUnion(cu, 31, 28)
 104         Bitfield<31> cu3;
 105         Bitfield<30> cu2;
 106         Bitfield<29> cu1;
 107         Bitfield<28> cu0;
 108     EndSubBitUnion(cu)
 109     Bitfield<27>     rp;
 110     Bitfield<26>     fr;
 111     Bitfield<25>     re;
 112     Bitfield<24>     mx;
 113     Bitfield<23>     px;
 114     Bitfield<22>     bev;
 115     Bitfield<21>     ts;
 116     Bitfield<20>     sr;
 117     Bitfield<19>     nmi;
 118     // Bit 18 is zero
 119     Bitfield<17, 16> impl;
 120     Bitfield<15, 10> ipl;
 121     SubBitUnion(im, 15, 8)
 122         Bitfield<15> im7;
 123         Bitfield<14> im6;
 124         Bitfield<13> im5;
 125         Bitfield<12> im4;
 126         Bitfield<11> im3;
 127         Bitfield<10> im2;
 128         Bitfield<9>  im1;
 129         Bitfield<8>  im0;
 130     EndSubBitUnion(im)
 131     Bitfield<7>      kx;
 132     Bitfield<6>      sx;
 133     Bitfield<5>      ux;
 134     Bitfield<4,  3>  ksu;
 135     Bitfield<4>      um;
 136     Bitfield<3>      r0;
 137     Bitfield<2>      erl;
 138     Bitfield<1>      exl;
 139     Bitfield<0>      ie;
 140 EndBitUnion(StatusReg)
 141
 142 BitUnion32(IntCtlReg)
 143     Bitfield<31, 29> ipti;
 144     Bitfield<28, 26> ippci;
 145     // Bits 26-10 are zeros
 146     Bitfield<9,  5>  vs;
 147     // Bits 4-0 are zeros
 148 EndBitUnion(IntCtlReg)
 149
 150 BitUnion32(SRSCtlReg)
 151     // Bits 31-30 are zeros
 152     Bitfield<29, 26> hss;
 153     // Bits 25-22 are zeros
 154     Bitfield<21, 18> eicss;
 155     // Bits 17-16 are zeros
 156     Bitfield<15, 12> ess;
 157     // Bits 11-10 are zeros
 158     Bitfield<9,  6>  pss;
 159     // Bits 5-4 are zeros
 160     Bitfield<3,  0>  css;
 161 EndBitUnion(SRSCtlReg)
 162
 163 BitUnion32(SRSMapReg)
 164     Bitfield<31, 28> ssv7;
 165     Bitfield<27, 24> ssv6;
 166     Bitfield<23, 20> ssv5;
 167     Bitfield<19, 16> ssv4;
 168     Bitfield<15, 12> ssv3;
 169     Bitfield<11, 8>  ssv2;
 170     Bitfield<7,  4>  ssv1;
 171     Bitfield<3,  0>  ssv0;
 172 EndBitUnion(SRSMapReg)
 173
 174 BitUnion32(CauseReg)
 175     Bitfield<31>     bd;
 176     Bitfield<30>     ti;
 177     Bitfield<29, 28> ce;
 178     Bitfield<27>     dc;
 179     Bitfield<26>     pci;
 180     // Bits 25-24 are zeros
 181     Bitfield<23>     iv;
 182     Bitfield<22>     wp;
 183     // Bits 21-16 are zeros
 184     Bitfield<15, 10> ripl;
 185     SubBitUnion(ip, 15, 8)
 186         Bitfield<15> ip7;
 187         Bitfield<14> ip6;
 188         Bitfield<13> ip5;
 189         Bitfield<12> ip4;
 190         Bitfield<11> ip3;
 191         Bitfield<10> ip2;
 192         Bitfield<9>  ip1;
 193         Bitfield<8>  ip0;
 194     EndSubBitUnion(ip);
 195     // Bit 7 is zero
 196     Bitfield<6,  2>  excCode;
 197     // Bits 1-0 are zeros
 198 EndBitUnion(CauseReg)
 199
 200 BitUnion32(PRIdReg)
 201     Bitfield<31, 24> coOp;
 202     Bitfield<23, 16> coId;
 203     Bitfield<15, 8>  procId;
 204     Bitfield<7,  0>  rev;
 205 EndBitUnion(PRIdReg)
 206
 207 BitUnion32(EBaseReg)
 208     // Bit 31 is one
 209     // Bit 30 is zero
 210     Bitfield<29, 12> exceptionBase;
 211     // Bits 11-10 are zeros
 212     Bitfield<9,  9>  cpuNum;
 213 EndBitUnion(EBaseReg)
 214
 215 BitUnion32(ConfigReg)
 216     Bitfield<31>     m;
 217     Bitfield<30, 28> k23;
 218     Bitfield<27, 25> ku;
 219     Bitfield<24, 16> impl;
 220     Bitfield<15>     be;
 221     Bitfield<14, 13> at;
 222     Bitfield<12, 10> ar;
 223     Bitfield<9,  7>  mt;
 224     // Bits 6-4 are zeros
 225     Bitfield<3>      vi;
 226     Bitfield<2,  0>  k0;
 227 EndBitUnion(ConfigReg)
 228
 229 BitUnion32(Config1Reg)
 230     Bitfield<31>     m;
 231     Bitfield<30, 25> mmuSize;
 232     Bitfield<24, 22> is;
 233     Bitfield<21, 19> il;
 234     Bitfield<18, 16> ia;
 235     Bitfield<15, 13> ds;
 236     Bitfield<12, 10> dl;
 237     Bitfield<9,  7>  da;
 238     Bitfield<6>      c2;
 239     Bitfield<5>      md;
 240     Bitfield<4>      pc;
 241     Bitfield<3>      wr;
 242     Bitfield<2>      ca;
 243     Bitfield<1>      ep;
 244     Bitfield<0>      fp;
 245 EndBitUnion(Config1Reg)
 246
 247 BitUnion32(Config2Reg)
 248     Bitfield<31>     m;
 249     Bitfield<30, 28> tu;
 250     Bitfield<27, 24> ts;
 251     Bitfield<23, 20> tl;
 252     Bitfield<19, 16> ta;
 253     Bitfield<15, 12> su;
 254     Bitfield<11, 8>  ss;
 255     Bitfield<7,  4>  sl;
 256     Bitfield<3,  0>  sa;
 257 EndBitUnion(Config2Reg)
 258
 259 BitUnion32(Config3Reg)
 260     Bitfield<31> m;
 261     // Bits 30-11 are zeros
 262     Bitfield<10> dspp;
 263     // Bits 9-8 are zeros
 264     Bitfield<7>  lpa;
 265     Bitfield<6>  veic;
 266     Bitfield<5>  vint;
 267     Bitfield<4>  sp;
 268     // Bit 3 is zero
 269     Bitfield<2>  mt;
 270     Bitfield<1>  sm;
 271     Bitfield<0>  tl;
 272 EndBitUnion(Config3Reg)
 273
 274 BitUnion64(WatchLoReg)
 275     Bitfield<63, 3> vaddr;
 276     Bitfield<2>     i;
 277     Bitfield<1>     r;
 278     Bitfield<0>     w;
 279 EndBitUnion(WatchLoReg)
 280
 281 BitUnion32(WatchHiReg)
 282     Bitfield<31>     m;
 283     Bitfield<30>     g;
 284     // Bits 29-24 are zeros
 285     Bitfield<23, 16> asid;
 286     // Bits 15-12 are zeros
 287     Bitfield<11, 3>  mask;
 288     Bitfield<2>      i;
 289     Bitfield<1>      r;
 290     Bitfield<0>      w;
 291 EndBitUnion(WatchHiReg)
 292
 293 BitUnion32(PerfCntCtlReg)
 294     Bitfield<31>    m;
 295     Bitfield<30>    w;
 296     // Bits 29-11 are zeros
 297     Bitfield<10, 5> event;
 298     Bitfield<4>     ie;
 299     Bitfield<3>     u;
 300     Bitfield<2>     s;
 301     Bitfield<1>     k;
 302     Bitfield<0>     exl;
 303 EndBitUnion(PerfCntCtlReg)
 304
 305 BitUnion32(CacheErrReg)
 306     Bitfield<31>     er;
 307     Bitfield<30>     ec;
 308     Bitfield<29>     ed;
 309     Bitfield<28>     et;
 310     Bitfield<27>     es;
 311     Bitfield<26>     ee;
 312     Bitfield<25>     eb;
 313     Bitfield<24, 22> impl;
 314     Bitfield<22, 0>  index;
 315 EndBitUnion(CacheErrReg)
 316
 317 BitUnion32(TagLoReg)
 318     Bitfield<31, 8> pTagLo;
 319     Bitfield<7,  6> pState;
 320     Bitfield<5>     l;
 321     Bitfield<4,  3> impl;
 322     // Bits 2-1 are zeros
 323     Bitfield<0>     p;
 324 EndBitUnion(TagLoReg)
 325
 326 } // namespace RiscvISA
 327
 328 #endif