src/arch/riscv/process.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * Copyright (c) 2016 The University of Virginia
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #include "arch/riscv/process.hh"
  31
  32 #include <algorithm>
  33 #include <cstddef>
  34 #include <iostream>
  35 #include <iterator>
  36 #include <map>
  37 #include <string>
  38 #include <vector>
  39
  40 #include "arch/riscv/isa.hh"
  41 #include "arch/riscv/isa_traits.hh"
  42 #include "arch/riscv/registers.hh"
  43 #include "base/loader/elf_object.hh"
  44 #include "base/loader/object_file.hh"
  45 #include "base/logging.hh"
  46 #include "base/random.hh"
  47 #include "cpu/thread_context.hh"
  48 #include "debug/Stack.hh"
  49 #include "mem/page_table.hh"
  50 #include "params/Process.hh"
  51 #include "sim/aux_vector.hh"
  52 #include "sim/process.hh"
  53 #include "sim/process_impl.hh"
  54 #include "sim/syscall_return.hh"
  55 #include "sim/system.hh"
  56
  57 using namespace std;
  58 using namespace RiscvISA;
  59
  60 RiscvProcess::RiscvProcess(ProcessParams *params, ObjectFile *objFile) :
  61         Process(params,
  62                 new EmulationPageTable(params->name, params->pid, PageBytes),
  63                 objFile)
  64 {
  65     fatal_if(params->useArchPT, "Arch page tables not implemented.");
  66 }
  67
  68 RiscvProcess64::RiscvProcess64(ProcessParams *params, ObjectFile *objFile) :
  69         RiscvProcess(params, objFile)
  70 {
  71     const Addr stack_base = 0x7FFFFFFFFFFFFFFFL;
  72     const Addr max_stack_size = 8 * 1024 * 1024;
  73     const Addr next_thread_stack_base = stack_base - max_stack_size;
  74     const Addr brk_point = roundUp(image.maxAddr(), PageBytes);
  75     const Addr mmap_end = 0x4000000000000000L;
  76     memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
  77             next_thread_stack_base, mmap_end);
  78 }
  79
  80 RiscvProcess32::RiscvProcess32(ProcessParams *params, ObjectFile *objFile) :
  81         RiscvProcess(params, objFile)
  82 {
  83     const Addr stack_base = 0x7FFFFFFF;
  84     const Addr max_stack_size = 8 * 1024 * 1024;
  85     const Addr next_thread_stack_base = stack_base - max_stack_size;
  86     const Addr brk_point = roundUp(image.maxAddr(), PageBytes);
  87     const Addr mmap_end = 0x40000000L;
  88     memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
  89                                      next_thread_stack_base, mmap_end);
  90 }
  91
  92 void
  93 RiscvProcess64::initState()
  94 {
  95     Process::initState();
  96
  97     argsInit<uint64_t>(PageBytes);
  98     for (ContextID ctx: contextIds)
  99         system->getThreadContext(ctx)->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
 100 }
 101
 102 void
 103 RiscvProcess32::initState()
 104 {
 105     Process::initState();
 106
 107     argsInit<uint32_t>(PageBytes);
 108     for (ContextID ctx: contextIds) {
 109         system->getThreadContext(ctx)->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
 110         PCState pc = system->getThreadContext(ctx)->pcState();
 111         pc.rv32(true);
 112         system->getThreadContext(ctx)->pcState(pc);
 113     }
 114 }
 115
 116 template<class IntType> void
 117 RiscvProcess::argsInit(int pageSize)
 118 {
 119     const int RandomBytes = 16;
 120     const int addrSize = sizeof(IntType);
 121
 122     ElfObject* elfObject = dynamic_cast<ElfObject*>(objFile);
 123     memState->setStackMin(memState->getStackBase());
 124
 125     // Determine stack size and populate auxv
 126     Addr stack_top = memState->getStackMin();
 127     stack_top -= RandomBytes;
 128     for (const string& arg: argv)
 129         stack_top -= arg.size() + 1;
 130     for (const string& env: envp)
 131         stack_top -= env.size() + 1;
 132     stack_top &= -addrSize;
 133
 134     vector<AuxVector<IntType>> auxv;
 135     if (elfObject != nullptr) {
 136         auxv.emplace_back(M5_AT_ENTRY, objFile->entryPoint());
 137         auxv.emplace_back(M5_AT_PHNUM, elfObject->programHeaderCount());
 138         auxv.emplace_back(M5_AT_PHENT, elfObject->programHeaderSize());
 139         auxv.emplace_back(M5_AT_PHDR, elfObject->programHeaderTable());
 140         auxv.emplace_back(M5_AT_PAGESZ, PageBytes);
 141         auxv.emplace_back(M5_AT_SECURE, 0);
 142         auxv.emplace_back(M5_AT_RANDOM, stack_top);
 143         auxv.emplace_back(M5_AT_NULL, 0);
 144     }
 145     stack_top -= (1 + argv.size()) * addrSize +
 146                    (1 + envp.size()) * addrSize +
 147                    addrSize + 2 * sizeof(IntType) * auxv.size();
 148     stack_top &= -2*addrSize;
 149     memState->setStackSize(memState->getStackBase() - stack_top);
 150     allocateMem(roundDown(stack_top, pageSize),
 151             roundUp(memState->getStackSize(), pageSize));
 152
 153     // Copy random bytes (for AT_RANDOM) to stack
 154     memState->setStackMin(memState->getStackMin() - RandomBytes);
 155     uint8_t at_random[RandomBytes];
 156     generate(begin(at_random), end(at_random),
 157              [&]{ return random_mt.random(0, 0xFF); });
 158     initVirtMem.writeBlob(memState->getStackMin(), at_random, RandomBytes);
 159
 160     // Copy argv to stack
 161     vector<Addr> argPointers;
 162     for (const string& arg: argv) {
 163         memState->setStackMin(memState->getStackMin() - (arg.size() + 1));
 164         initVirtMem.writeString(memState->getStackMin(), arg.c_str());
 165         argPointers.push_back(memState->getStackMin());
 166         if (DTRACE(Stack)) {
 167             string wrote;
 168             initVirtMem.readString(wrote, argPointers.back());
 169             DPRINTFN("Wrote arg \"%s\" to address %p\n",
 170                     wrote, (void*)memState->getStackMin());
 171         }
 172     }
 173     argPointers.push_back(0);
 174
 175     // Copy envp to stack
 176     vector<Addr> envPointers;
 177     for (const string& env: envp) {
 178         memState->setStackMin(memState->getStackMin() - (env.size() + 1));
 179         initVirtMem.writeString(memState->getStackMin(), env.c_str());
 180         envPointers.push_back(memState->getStackMin());
 181         DPRINTF(Stack, "Wrote env \"%s\" to address %p\n",
 182                 env, (void*)memState->getStackMin());
 183     }
 184     envPointers.push_back(0);
 185
 186     // Align stack
 187     memState->setStackMin(memState->getStackMin() & -addrSize);
 188
 189     // Calculate bottom of stack
 190     memState->setStackMin(memState->getStackMin() -
 191             ((1 + argv.size()) * addrSize +
 192              (1 + envp.size()) * addrSize +
 193              addrSize + 2 * sizeof(IntType) * auxv.size()));
 194     memState->setStackMin(memState->getStackMin() & (-2 * addrSize));
 195     Addr sp = memState->getStackMin();
 196     const auto pushOntoStack =
 197         [this, &sp](IntType data) {
 198             initVirtMem.write(sp, data, GuestByteOrder);
 199             sp += sizeof(data);
 200         };
 201
 202     // Push argc and argv pointers onto stack
 203     IntType argc = argv.size();
 204     DPRINTF(Stack, "Wrote argc %d to address %#x\n", argc, sp);
 205     pushOntoStack(argc);
 206
 207     for (const Addr& argPointer: argPointers) {
 208         DPRINTF(Stack, "Wrote argv pointer %#x to address %#x\n",
 209                 argPointer, sp);
 210         pushOntoStack(argPointer);
 211     }
 212
 213     // Push env pointers onto stack
 214     for (const Addr& envPointer: envPointers) {
 215         DPRINTF(Stack, "Wrote envp pointer %#x to address %#x\n",
 216                 envPointer, sp);
 217         pushOntoStack(envPointer);
 218     }
 219
 220     // Push aux vector onto stack
 221     std::map<IntType, string> aux_keys = {
 222         {M5_AT_ENTRY, "M5_AT_ENTRY"},
 223         {M5_AT_PHNUM, "M5_AT_PHNUM"},
 224         {M5_AT_PHENT, "M5_AT_PHENT"},
 225         {M5_AT_PHDR, "M5_AT_PHDR"},
 226         {M5_AT_PAGESZ, "M5_AT_PAGESZ"},
 227         {M5_AT_SECURE, "M5_AT_SECURE"},
 228         {M5_AT_RANDOM, "M5_AT_RANDOM"},
 229         {M5_AT_NULL, "M5_AT_NULL"}
 230     };
 231     for (const auto &aux: auxv) {
 232         DPRINTF(Stack, "Wrote aux key %s to address %#x\n",
 233                 aux_keys[aux.type], sp);
 234         pushOntoStack(aux.type);
 235         DPRINTF(Stack, "Wrote aux value %x to address %#x\n", aux.val, sp);
 236         pushOntoStack(aux.val);
 237     }
 238
 239     ThreadContext *tc = system->getThreadContext(contextIds[0]);
 240     tc->setIntReg(StackPointerReg, memState->getStackMin());
 241     tc->pcState(getStartPC());
 242
 243     memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
 244 }
 245
 246 RegVal
 247 RiscvProcess::getSyscallArg(ThreadContext *tc, int &i)
 248 {
 249     // If a larger index is requested than there are syscall argument
 250     // registers, return 0
 251     RegVal retval = 0;
 252     if (i < SyscallArgumentRegs.size())
 253         retval = tc->readIntReg(SyscallArgumentRegs[i]);
 254     i++;
 255     return retval;
 256 }
 257
 258 void
 259 RiscvProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
 260 {
 261     if (sysret.successful()) {
 262         // no error
 263         tc->setIntReg(SyscallPseudoReturnReg, sysret.returnValue());
 264     } else {
 265         // got an error, return details
 266         tc->setIntReg(SyscallPseudoReturnReg, sysret.encodedValue());
 267     }
 268 }