src/arch/riscv/process.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * Copyright (c) 2016 The University of Virginia
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * Authors: Gabe Black
  30  *          Ali Saidi
  31  *          Korey Sewell
  32  *          Alec Roelke
  33  */
  34 #include "arch/riscv/process.hh"
  35
  36 #include <algorithm>
  37 #include <cstddef>
  38 #include <iostream>
  39 #include <iterator>
  40 #include <map>
  41 #include <string>
  42 #include <vector>
  43
  44 #include "arch/riscv/isa.hh"
  45 #include "arch/riscv/isa_traits.hh"
  46 #include "arch/riscv/registers.hh"
  47 #include "base/loader/elf_object.hh"
  48 #include "base/loader/object_file.hh"
  49 #include "base/logging.hh"
  50 #include "base/random.hh"
  51 #include "cpu/thread_context.hh"
  52 #include "debug/Stack.hh"
  53 #include "mem/page_table.hh"
  54 #include "params/Process.hh"
  55 #include "sim/aux_vector.hh"
  56 #include "sim/process.hh"
  57 #include "sim/process_impl.hh"
  58 #include "sim/syscall_return.hh"
  59 #include "sim/system.hh"
  60
  61 using namespace std;
  62 using namespace RiscvISA;
  63
  64 RiscvProcess::RiscvProcess(ProcessParams *params, ObjectFile *objFile) :
  65         Process(params,
  66                 new EmulationPageTable(params->name, params->pid, PageBytes),
  67                 objFile)
  68 {
  69     fatal_if(params->useArchPT, "Arch page tables not implemented.");
  70 }
  71
  72 RiscvProcess64::RiscvProcess64(ProcessParams *params, ObjectFile *objFile) :
  73         RiscvProcess(params, objFile)
  74 {
  75     const Addr stack_base = 0x7FFFFFFFFFFFFFFFL;
  76     const Addr max_stack_size = 8 * 1024 * 1024;
  77     const Addr next_thread_stack_base = stack_base - max_stack_size;
  78     const Addr brk_point = roundUp(image.maxAddr(), PageBytes);
  79     const Addr mmap_end = 0x4000000000000000L;
  80     memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
  81             next_thread_stack_base, mmap_end);
  82 }
  83
  84 RiscvProcess32::RiscvProcess32(ProcessParams *params, ObjectFile *objFile) :
  85         RiscvProcess(params, objFile)
  86 {
  87     const Addr stack_base = 0x7FFFFFFF;
  88     const Addr max_stack_size = 8 * 1024 * 1024;
  89     const Addr next_thread_stack_base = stack_base - max_stack_size;
  90     const Addr brk_point = roundUp(image.maxAddr(), PageBytes);
  91     const Addr mmap_end = 0x40000000L;
  92     memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
  93                                      next_thread_stack_base, mmap_end);
  94 }
  95
  96 void
  97 RiscvProcess64::initState()
  98 {
  99     Process::initState();
 100
 101     argsInit<uint64_t>(PageBytes);
 102     for (ContextID ctx: contextIds)
 103         system->getThreadContext(ctx)->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
 104 }
 105
 106 void
 107 RiscvProcess32::initState()
 108 {
 109     Process::initState();
 110
 111     argsInit<uint32_t>(PageBytes);
 112     for (ContextID ctx: contextIds) {
 113         system->getThreadContext(ctx)->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
 114         PCState pc = system->getThreadContext(ctx)->pcState();
 115         pc.rv32(true);
 116         system->getThreadContext(ctx)->pcState(pc);
 117     }
 118 }
 119
 120 template<class IntType> void
 121 RiscvProcess::argsInit(int pageSize)
 122 {
 123     const int RandomBytes = 16;
 124     const int addrSize = sizeof(IntType);
 125
 126     ElfObject* elfObject = dynamic_cast<ElfObject*>(objFile);
 127     memState->setStackMin(memState->getStackBase());
 128
 129     // Determine stack size and populate auxv
 130     Addr stack_top = memState->getStackMin();
 131     stack_top -= RandomBytes;
 132     for (const string& arg: argv)
 133         stack_top -= arg.size() + 1;
 134     for (const string& env: envp)
 135         stack_top -= env.size() + 1;
 136     stack_top &= -addrSize;
 137
 138     vector<AuxVector<IntType>> auxv;
 139     if (elfObject != nullptr) {
 140         auxv.emplace_back(M5_AT_ENTRY, objFile->entryPoint());
 141         auxv.emplace_back(M5_AT_PHNUM, elfObject->programHeaderCount());
 142         auxv.emplace_back(M5_AT_PHENT, elfObject->programHeaderSize());
 143         auxv.emplace_back(M5_AT_PHDR, elfObject->programHeaderTable());
 144         auxv.emplace_back(M5_AT_PAGESZ, PageBytes);
 145         auxv.emplace_back(M5_AT_SECURE, 0);
 146         auxv.emplace_back(M5_AT_RANDOM, stack_top);
 147         auxv.emplace_back(M5_AT_NULL, 0);
 148     }
 149     stack_top -= (1 + argv.size()) * addrSize +
 150                    (1 + envp.size()) * addrSize +
 151                    addrSize + 2 * sizeof(IntType) * auxv.size();
 152     stack_top &= -2*addrSize;
 153     memState->setStackSize(memState->getStackBase() - stack_top);
 154     allocateMem(roundDown(stack_top, pageSize),
 155             roundUp(memState->getStackSize(), pageSize));
 156
 157     // Copy random bytes (for AT_RANDOM) to stack
 158     memState->setStackMin(memState->getStackMin() - RandomBytes);
 159     uint8_t at_random[RandomBytes];
 160     generate(begin(at_random), end(at_random),
 161              [&]{ return random_mt.random(0, 0xFF); });
 162     initVirtMem.writeBlob(memState->getStackMin(), at_random, RandomBytes);
 163
 164     // Copy argv to stack
 165     vector<Addr> argPointers;
 166     for (const string& arg: argv) {
 167         memState->setStackMin(memState->getStackMin() - (arg.size() + 1));
 168         initVirtMem.writeString(memState->getStackMin(), arg.c_str());
 169         argPointers.push_back(memState->getStackMin());
 170         if (DTRACE(Stack)) {
 171             string wrote;
 172             initVirtMem.readString(wrote, argPointers.back());
 173             DPRINTFN("Wrote arg \"%s\" to address %p\n",
 174                     wrote, (void*)memState->getStackMin());
 175         }
 176     }
 177     argPointers.push_back(0);
 178
 179     // Copy envp to stack
 180     vector<Addr> envPointers;
 181     for (const string& env: envp) {
 182         memState->setStackMin(memState->getStackMin() - (env.size() + 1));
 183         initVirtMem.writeString(memState->getStackMin(), env.c_str());
 184         envPointers.push_back(memState->getStackMin());
 185         DPRINTF(Stack, "Wrote env \"%s\" to address %p\n",
 186                 env, (void*)memState->getStackMin());
 187     }
 188     envPointers.push_back(0);
 189
 190     // Align stack
 191     memState->setStackMin(memState->getStackMin() & -addrSize);
 192
 193     // Calculate bottom of stack
 194     memState->setStackMin(memState->getStackMin() -
 195             ((1 + argv.size()) * addrSize +
 196              (1 + envp.size()) * addrSize +
 197              addrSize + 2 * sizeof(IntType) * auxv.size()));
 198     memState->setStackMin(memState->getStackMin() & (-2 * addrSize));
 199     Addr sp = memState->getStackMin();
 200     const auto pushOntoStack =
 201         [this, &sp](IntType data) {
 202             initVirtMem.write(sp, data, GuestByteOrder);
 203             sp += sizeof(data);
 204         };
 205
 206     // Push argc and argv pointers onto stack
 207     IntType argc = argv.size();
 208     DPRINTF(Stack, "Wrote argc %d to address %#x\n", argc, sp);
 209     pushOntoStack(argc);
 210
 211     for (const Addr& argPointer: argPointers) {
 212         DPRINTF(Stack, "Wrote argv pointer %#x to address %#x\n",
 213                 argPointer, sp);
 214         pushOntoStack(argPointer);
 215     }
 216
 217     // Push env pointers onto stack
 218     for (const Addr& envPointer: envPointers) {
 219         DPRINTF(Stack, "Wrote envp pointer %#x to address %#x\n",
 220                 envPointer, sp);
 221         pushOntoStack(envPointer);
 222     }
 223
 224     // Push aux vector onto stack
 225     std::map<IntType, string> aux_keys = {
 226         {M5_AT_ENTRY, "M5_AT_ENTRY"},
 227         {M5_AT_PHNUM, "M5_AT_PHNUM"},
 228         {M5_AT_PHENT, "M5_AT_PHENT"},
 229         {M5_AT_PHDR, "M5_AT_PHDR"},
 230         {M5_AT_PAGESZ, "M5_AT_PAGESZ"},
 231         {M5_AT_SECURE, "M5_AT_SECURE"},
 232         {M5_AT_RANDOM, "M5_AT_RANDOM"},
 233         {M5_AT_NULL, "M5_AT_NULL"}
 234     };
 235     for (const auto &aux: auxv) {
 236         DPRINTF(Stack, "Wrote aux key %s to address %#x\n",
 237                 aux_keys[aux.type], sp);
 238         pushOntoStack(aux.type);
 239         DPRINTF(Stack, "Wrote aux value %x to address %#x\n", aux.val, sp);
 240         pushOntoStack(aux.val);
 241     }
 242
 243     ThreadContext *tc = system->getThreadContext(contextIds[0]);
 244     tc->setIntReg(StackPointerReg, memState->getStackMin());
 245     tc->pcState(getStartPC());
 246
 247     memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
 248 }
 249
 250 RegVal
 251 RiscvProcess::getSyscallArg(ThreadContext *tc, int &i)
 252 {
 253     // If a larger index is requested than there are syscall argument
 254     // registers, return 0
 255     RegVal retval = 0;
 256     if (i < SyscallArgumentRegs.size())
 257         retval = tc->readIntReg(SyscallArgumentRegs[i]);
 258     i++;
 259     return retval;
 260 }
 261
 262 void
 263 RiscvProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val)
 264 {
 265     tc->setIntReg(SyscallArgumentRegs[i], val);
 266 }
 267
 268 void
 269 RiscvProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
 270 {
 271     if (sysret.successful()) {
 272         // no error
 273         tc->setIntReg(SyscallPseudoReturnReg, sysret.returnValue());
 274     } else {
 275         // got an error, return details
 276         tc->setIntReg(SyscallPseudoReturnReg, sysret.encodedValue());
 277     }
 278 }