src/arch/riscv/registers.hh

   1 /*
   2  * Copyright (c) 2013 ARM Limited
   3  * Copyright (c) 2014-2015 Sven Karlsson
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2016 RISC-V Foundation
  16  * Copyright (c) 2016 The University of Virginia
  17  * All rights reserved.
  18  *
  19  * Redistribution and use in source and binary forms, with or without
  20  * modification, are permitted provided that the following conditions are
  21  * met: redistributions of source code must retain the above copyright
  22  * notice, this list of conditions and the following disclaimer;
  23  * redistributions in binary form must reproduce the above copyright
  24  * notice, this list of conditions and the following disclaimer in the
  25  * documentation and/or other materials provided with the distribution;
  26  * neither the name of the copyright holders nor the names of its
  27  * contributors may be used to endorse or promote products derived from
  28  * this software without specific prior written permission.
  29  *
  30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  31  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  32  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  33  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  34  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  35  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  36  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  37  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  38  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  39  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  40  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  41  *
  42  * Authors: Andreas Hansson
  43  *          Sven Karlsson
  44  *          Alec Roelke
  45  */
  46
  47 #ifndef __ARCH_RISCV_REGISTERS_HH__
  48 #define __ARCH_RISCV_REGISTERS_HH__
  49
  50 #include <map>
  51 #include <string>
  52 #include <vector>
  53
  54 #include "arch/generic/types.hh"
  55 #include "arch/generic/vec_pred_reg.hh"
  56 #include "arch/generic/vec_reg.hh"
  57 #include "arch/isa_traits.hh"
  58 #include "arch/riscv/generated/max_inst_regs.hh"
  59 #include "base/types.hh"
  60
  61 namespace RiscvISA {
  62
  63 using RiscvISAInst::MaxInstSrcRegs;
  64 using RiscvISAInst::MaxInstDestRegs;
  65 const int MaxMiscDestRegs = 1;
  66
  67 typedef RegVal IntReg;
  68 typedef RegVal FloatReg;
  69 typedef uint8_t CCReg; // Not applicable to Riscv
  70 typedef RegVal MiscReg;
  71
  72 // Not applicable to RISC-V
  73 using VecElem = ::DummyVecElem;
  74 using VecReg = ::DummyVecReg;
  75 using ConstVecReg = ::DummyConstVecReg;
  76 using VecRegContainer = ::DummyVecRegContainer;
  77 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
  78 constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;
  79
  80 // Not applicable to RISC-V
  81 using VecPredReg = ::DummyVecPredReg;
  82 using ConstVecPredReg = ::DummyConstVecPredReg;
  83 using VecPredRegContainer = ::DummyVecPredRegContainer;
  84 constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
  85 constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
  86
  87 const int NumIntArchRegs = 32;
  88 const int NumMicroIntRegs = 1;
  89 const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs;
  90 const int NumFloatRegs = 32;
  91
  92 const unsigned NumVecRegs = 1;  // Not applicable to RISC-V
  93                                 // (1 to prevent warnings)
  94 const int NumVecPredRegs = 1;  // Not applicable to RISC-V
  95                                // (1 to prevent warnings)
  96
  97 const int NumCCRegs = 0;
  98
  99 // Semantically meaningful register indices
 100 const int ZeroReg = 0;
 101 const int ReturnAddrReg = 1;
 102 const int StackPointerReg = 2;
 103 const int GlobalPointerReg = 3;
 104 const int ThreadPointerReg = 4;
 105 const int FramePointerReg = 8;
 106 const int ReturnValueReg = 10;
 107 const std::vector<int> ReturnValueRegs = {10, 11};
 108 const std::vector<int> ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17};
 109 const int AMOTempReg = 32;
 110
 111 const int SyscallPseudoReturnReg = 10;
 112 const std::vector<int> SyscallArgumentRegs = {10, 11, 12, 13, 14, 15, 16};
 113 const int SyscallNumReg = 17;
 114
 115 const std::vector<std::string> IntRegNames = {
 116     "zero", "ra", "sp", "gp",
 117     "tp", "t0", "t1", "t2",
 118     "s0", "s1", "a0", "a1",
 119     "a2", "a3", "a4", "a5",
 120     "a6", "a7", "s2", "s3",
 121     "s4", "s5", "s6", "s7",
 122     "s8", "s9", "s10", "s11",
 123     "t3", "t4", "t5", "t6"
 124 };
 125 const std::vector<std::string> FloatRegNames = {
 126     "ft0", "ft1", "ft2", "ft3",
 127     "ft4", "ft5", "ft6", "ft7",
 128     "fs0", "fs1", "fa0", "fa1",
 129     "fa2", "fa3", "fa4", "fa5",
 130     "fa6", "fa7", "fs2", "fs3",
 131     "fs4", "fs5", "fs6", "fs7",
 132     "fs8", "fs9", "fs10", "fs11",
 133     "ft8", "ft9", "ft10", "ft11"
 134 };
 135
 136 enum MiscRegIndex {
 137     MISCREG_PRV = 0,
 138     MISCREG_ISA,
 139     MISCREG_VENDORID,
 140     MISCREG_ARCHID,
 141     MISCREG_IMPID,
 142     MISCREG_HARTID,
 143     MISCREG_STATUS,
 144     MISCREG_IP,
 145     MISCREG_IE,
 146     MISCREG_CYCLE,
 147     MISCREG_TIME,
 148     MISCREG_INSTRET,
 149     MISCREG_HPMCOUNTER03,
 150     MISCREG_HPMCOUNTER04,
 151     MISCREG_HPMCOUNTER05,
 152     MISCREG_HPMCOUNTER06,
 153     MISCREG_HPMCOUNTER07,
 154     MISCREG_HPMCOUNTER08,
 155     MISCREG_HPMCOUNTER09,
 156     MISCREG_HPMCOUNTER10,
 157     MISCREG_HPMCOUNTER11,
 158     MISCREG_HPMCOUNTER12,
 159     MISCREG_HPMCOUNTER13,
 160     MISCREG_HPMCOUNTER14,
 161     MISCREG_HPMCOUNTER15,
 162     MISCREG_HPMCOUNTER16,
 163     MISCREG_HPMCOUNTER17,
 164     MISCREG_HPMCOUNTER18,
 165     MISCREG_HPMCOUNTER19,
 166     MISCREG_HPMCOUNTER20,
 167     MISCREG_HPMCOUNTER21,
 168     MISCREG_HPMCOUNTER22,
 169     MISCREG_HPMCOUNTER23,
 170     MISCREG_HPMCOUNTER24,
 171     MISCREG_HPMCOUNTER25,
 172     MISCREG_HPMCOUNTER26,
 173     MISCREG_HPMCOUNTER27,
 174     MISCREG_HPMCOUNTER28,
 175     MISCREG_HPMCOUNTER29,
 176     MISCREG_HPMCOUNTER30,
 177     MISCREG_HPMCOUNTER31,
 178     MISCREG_HPMEVENT03,
 179     MISCREG_HPMEVENT04,
 180     MISCREG_HPMEVENT05,
 181     MISCREG_HPMEVENT06,
 182     MISCREG_HPMEVENT07,
 183     MISCREG_HPMEVENT08,
 184     MISCREG_HPMEVENT09,
 185     MISCREG_HPMEVENT10,
 186     MISCREG_HPMEVENT11,
 187     MISCREG_HPMEVENT12,
 188     MISCREG_HPMEVENT13,
 189     MISCREG_HPMEVENT14,
 190     MISCREG_HPMEVENT15,
 191     MISCREG_HPMEVENT16,
 192     MISCREG_HPMEVENT17,
 193     MISCREG_HPMEVENT18,
 194     MISCREG_HPMEVENT19,
 195     MISCREG_HPMEVENT20,
 196     MISCREG_HPMEVENT21,
 197     MISCREG_HPMEVENT22,
 198     MISCREG_HPMEVENT23,
 199     MISCREG_HPMEVENT24,
 200     MISCREG_HPMEVENT25,
 201     MISCREG_HPMEVENT26,
 202     MISCREG_HPMEVENT27,
 203     MISCREG_HPMEVENT28,
 204     MISCREG_HPMEVENT29,
 205     MISCREG_HPMEVENT30,
 206     MISCREG_HPMEVENT31,
 207     MISCREG_TSELECT,
 208     MISCREG_TDATA1,
 209     MISCREG_TDATA2,
 210     MISCREG_TDATA3,
 211     MISCREG_DCSR,
 212     MISCREG_DPC,
 213     MISCREG_DSCRATCH,
 214
 215     MISCREG_MEDELEG,
 216     MISCREG_MIDELEG,
 217     MISCREG_MTVEC,
 218     MISCREG_MCOUNTEREN,
 219     MISCREG_MSCRATCH,
 220     MISCREG_MEPC,
 221     MISCREG_MCAUSE,
 222     MISCREG_MTVAL,
 223     MISCREG_PMPCFG0,
 224     // pmpcfg1 rv32 only
 225     MISCREG_PMPCFG2,
 226     // pmpcfg3 rv32 only
 227     MISCREG_PMPADDR00,
 228     MISCREG_PMPADDR01,
 229     MISCREG_PMPADDR02,
 230     MISCREG_PMPADDR03,
 231     MISCREG_PMPADDR04,
 232     MISCREG_PMPADDR05,
 233     MISCREG_PMPADDR06,
 234     MISCREG_PMPADDR07,
 235     MISCREG_PMPADDR08,
 236     MISCREG_PMPADDR09,
 237     MISCREG_PMPADDR10,
 238     MISCREG_PMPADDR11,
 239     MISCREG_PMPADDR12,
 240     MISCREG_PMPADDR13,
 241     MISCREG_PMPADDR14,
 242     MISCREG_PMPADDR15,
 243
 244     MISCREG_SEDELEG,
 245     MISCREG_SIDELEG,
 246     MISCREG_STVEC,
 247     MISCREG_SCOUNTEREN,
 248     MISCREG_SSCRATCH,
 249     MISCREG_SEPC,
 250     MISCREG_SCAUSE,
 251     MISCREG_STVAL,
 252     MISCREG_SATP,
 253
 254     MISCREG_UTVEC,
 255     MISCREG_USCRATCH,
 256     MISCREG_UEPC,
 257     MISCREG_UCAUSE,
 258     MISCREG_UTVAL,
 259     MISCREG_FFLAGS,
 260     MISCREG_FRM,
 261
 262     NUM_MISCREGS
 263 };
 264 const int NumMiscRegs = NUM_MISCREGS;
 265
 266 enum CSRIndex {
 267     CSR_USTATUS = 0x000,
 268     CSR_UIE = 0x004,
 269     CSR_UTVEC = 0x005,
 270     CSR_USCRATCH = 0x040,
 271     CSR_UEPC = 0x041,
 272     CSR_UCAUSE = 0x042,
 273     CSR_UTVAL = 0x043,
 274     CSR_UIP = 0x044,
 275     CSR_FFLAGS = 0x001,
 276     CSR_FRM = 0x002,
 277     CSR_FCSR = 0x003,
 278     CSR_CYCLE = 0xC00,
 279     CSR_TIME = 0xC01,
 280     CSR_INSTRET = 0xC02,
 281     CSR_HPMCOUNTER03 = 0xC03,
 282     CSR_HPMCOUNTER04 = 0xC04,
 283     CSR_HPMCOUNTER05 = 0xC05,
 284     CSR_HPMCOUNTER06 = 0xC06,
 285     CSR_HPMCOUNTER07 = 0xC07,
 286     CSR_HPMCOUNTER08 = 0xC08,
 287     CSR_HPMCOUNTER09 = 0xC09,
 288     CSR_HPMCOUNTER10 = 0xC0A,
 289     CSR_HPMCOUNTER11 = 0xC0B,
 290     CSR_HPMCOUNTER12 = 0xC0C,
 291     CSR_HPMCOUNTER13 = 0xC0D,
 292     CSR_HPMCOUNTER14 = 0xC0E,
 293     CSR_HPMCOUNTER15 = 0xC0F,
 294     CSR_HPMCOUNTER16 = 0xC10,
 295     CSR_HPMCOUNTER17 = 0xC11,
 296     CSR_HPMCOUNTER18 = 0xC12,
 297     CSR_HPMCOUNTER19 = 0xC13,
 298     CSR_HPMCOUNTER20 = 0xC14,
 299     CSR_HPMCOUNTER21 = 0xC15,
 300     CSR_HPMCOUNTER22 = 0xC16,
 301     CSR_HPMCOUNTER23 = 0xC17,
 302     CSR_HPMCOUNTER24 = 0xC18,
 303     CSR_HPMCOUNTER25 = 0xC19,
 304     CSR_HPMCOUNTER26 = 0xC1A,
 305     CSR_HPMCOUNTER27 = 0xC1B,
 306     CSR_HPMCOUNTER28 = 0xC1C,
 307     CSR_HPMCOUNTER29 = 0xC1D,
 308     CSR_HPMCOUNTER30 = 0xC1E,
 309     CSR_HPMCOUNTER31 = 0xC1F,
 310     // HPMCOUNTERH rv32 only
 311
 312     CSR_SSTATUS = 0x100,
 313     CSR_SEDELEG = 0x102,
 314     CSR_SIDELEG = 0x103,
 315     CSR_SIE = 0x104,
 316     CSR_STVEC = 0x105,
 317     CSR_SSCRATCH = 0x140,
 318     CSR_SEPC = 0x141,
 319     CSR_SCAUSE = 0x142,
 320     CSR_STVAL = 0x143,
 321     CSR_SIP = 0x144,
 322     CSR_SATP = 0x180,
 323
 324     CSR_MVENDORID = 0xF11,
 325     CSR_MARCHID = 0xF12,
 326     CSR_MIMPID = 0xF13,
 327     CSR_MHARTID = 0xF14,
 328     CSR_MSTATUS = 0x300,
 329     CSR_MISA = 0x301,
 330     CSR_MEDELEG = 0x302,
 331     CSR_MIDELEG = 0x303,
 332     CSR_MIE = 0x304,
 333     CSR_MTVEC = 0x305,
 334     CSR_MSCRATCH = 0x340,
 335     CSR_MEPC = 0x341,
 336     CSR_MCAUSE = 0x342,
 337     CSR_MTVAL = 0x343,
 338     CSR_MIP = 0x344,
 339     CSR_PMPCFG0 = 0x3A0,
 340     // pmpcfg1 rv32 only
 341     CSR_PMPCFG2 = 0x3A2,
 342     // pmpcfg3 rv32 only
 343     CSR_PMPADDR00 = 0x3B0,
 344     CSR_PMPADDR01 = 0x3B1,
 345     CSR_PMPADDR02 = 0x3B2,
 346     CSR_PMPADDR03 = 0x3B3,
 347     CSR_PMPADDR04 = 0x3B4,
 348     CSR_PMPADDR05 = 0x3B5,
 349     CSR_PMPADDR06 = 0x3B6,
 350     CSR_PMPADDR07 = 0x3B7,
 351     CSR_PMPADDR08 = 0x3B8,
 352     CSR_PMPADDR09 = 0x3B9,
 353     CSR_PMPADDR10 = 0x3BA,
 354     CSR_PMPADDR11 = 0x3BB,
 355     CSR_PMPADDR12 = 0x3BC,
 356     CSR_PMPADDR13 = 0x3BD,
 357     CSR_PMPADDR14 = 0x3BE,
 358     CSR_PMPADDR15 = 0x3BF,
 359     CSR_MCYCLE = 0xB00,
 360     CSR_MINSTRET = 0xB02,
 361     CSR_MHPMCOUNTER03 = 0xC03,
 362     CSR_MHPMCOUNTER04 = 0xC04,
 363     CSR_MHPMCOUNTER05 = 0xC05,
 364     CSR_MHPMCOUNTER06 = 0xC06,
 365     CSR_MHPMCOUNTER07 = 0xC07,
 366     CSR_MHPMCOUNTER08 = 0xC08,
 367     CSR_MHPMCOUNTER09 = 0xC09,
 368     CSR_MHPMCOUNTER10 = 0xC0A,
 369     CSR_MHPMCOUNTER11 = 0xC0B,
 370     CSR_MHPMCOUNTER12 = 0xC0C,
 371     CSR_MHPMCOUNTER13 = 0xC0D,
 372     CSR_MHPMCOUNTER14 = 0xC0E,
 373     CSR_MHPMCOUNTER15 = 0xC0F,
 374     CSR_MHPMCOUNTER16 = 0xC10,
 375     CSR_MHPMCOUNTER17 = 0xC11,
 376     CSR_MHPMCOUNTER18 = 0xC12,
 377     CSR_MHPMCOUNTER19 = 0xC13,
 378     CSR_MHPMCOUNTER20 = 0xC14,
 379     CSR_MHPMCOUNTER21 = 0xC15,
 380     CSR_MHPMCOUNTER22 = 0xC16,
 381     CSR_MHPMCOUNTER23 = 0xC17,
 382     CSR_MHPMCOUNTER24 = 0xC18,
 383     CSR_MHPMCOUNTER25 = 0xC19,
 384     CSR_MHPMCOUNTER26 = 0xC1A,
 385     CSR_MHPMCOUNTER27 = 0xC1B,
 386     CSR_MHPMCOUNTER28 = 0xC1C,
 387     CSR_MHPMCOUNTER29 = 0xC1D,
 388     CSR_MHPMCOUNTER30 = 0xC1E,
 389     CSR_MHPMCOUNTER31 = 0xC1F,
 390     // MHPMCOUNTERH rv32 only
 391     CSR_MHPMEVENT03 = 0x323,
 392     CSR_MHPMEVENT04 = 0x324,
 393     CSR_MHPMEVENT05 = 0x325,
 394     CSR_MHPMEVENT06 = 0x326,
 395     CSR_MHPMEVENT07 = 0x327,
 396     CSR_MHPMEVENT08 = 0x328,
 397     CSR_MHPMEVENT09 = 0x329,
 398     CSR_MHPMEVENT10 = 0x32A,
 399     CSR_MHPMEVENT11 = 0x32B,
 400     CSR_MHPMEVENT12 = 0x32C,
 401     CSR_MHPMEVENT13 = 0x32D,
 402     CSR_MHPMEVENT14 = 0x32E,
 403     CSR_MHPMEVENT15 = 0x32F,
 404     CSR_MHPMEVENT16 = 0x330,
 405     CSR_MHPMEVENT17 = 0x331,
 406     CSR_MHPMEVENT18 = 0x332,
 407     CSR_MHPMEVENT19 = 0x333,
 408     CSR_MHPMEVENT20 = 0x334,
 409     CSR_MHPMEVENT21 = 0x335,
 410     CSR_MHPMEVENT22 = 0x336,
 411     CSR_MHPMEVENT23 = 0x337,
 412     CSR_MHPMEVENT24 = 0x338,
 413     CSR_MHPMEVENT25 = 0x339,
 414     CSR_MHPMEVENT26 = 0x33A,
 415     CSR_MHPMEVENT27 = 0x33B,
 416     CSR_MHPMEVENT28 = 0x33C,
 417     CSR_MHPMEVENT29 = 0x33D,
 418     CSR_MHPMEVENT30 = 0x33E,
 419     CSR_MHPMEVENT31 = 0x33F,
 420
 421     CSR_TSELECT = 0x7A0,
 422     CSR_TDATA1 = 0x7A1,
 423     CSR_TDATA2 = 0x7A2,
 424     CSR_TDATA3 = 0x7A3,
 425     CSR_DCSR = 0x7B0,
 426     CSR_DPC = 0x7B1,
 427     CSR_DSCRATCH = 0x7B2
 428 };
 429
 430 struct CSRMetadata
 431 {
 432     const std::string name;
 433     const int physIndex;
 434 };
 435
 436 const std::map<int, CSRMetadata> CSRData = {
 437     {CSR_USTATUS, {"ustatus", MISCREG_STATUS}},
 438     {CSR_UIE, {"uie", MISCREG_IE}},
 439     {CSR_UTVEC, {"utvec", MISCREG_UTVEC}},
 440     {CSR_USCRATCH, {"uscratch", MISCREG_USCRATCH}},
 441     {CSR_UEPC, {"uepc", MISCREG_UEPC}},
 442     {CSR_UCAUSE, {"ucause", MISCREG_UCAUSE}},
 443     {CSR_UTVAL, {"utval", MISCREG_UTVAL}},
 444     {CSR_UIP, {"uip", MISCREG_IP}},
 445     {CSR_FFLAGS, {"fflags", MISCREG_FFLAGS}},
 446     {CSR_FRM, {"frm", MISCREG_FRM}},
 447     {CSR_FCSR, {"fcsr", MISCREG_FFLAGS}}, // Actually FRM << 5 | FFLAGS
 448     {CSR_CYCLE, {"cycle", MISCREG_CYCLE}},
 449     {CSR_TIME, {"time", MISCREG_TIME}},
 450     {CSR_INSTRET, {"instret", MISCREG_INSTRET}},
 451     {CSR_HPMCOUNTER03, {"hpmcounter03", MISCREG_HPMCOUNTER03}},
 452     {CSR_HPMCOUNTER04, {"hpmcounter04", MISCREG_HPMCOUNTER04}},
 453     {CSR_HPMCOUNTER05, {"hpmcounter05", MISCREG_HPMCOUNTER05}},
 454     {CSR_HPMCOUNTER06, {"hpmcounter06", MISCREG_HPMCOUNTER06}},
 455     {CSR_HPMCOUNTER07, {"hpmcounter07", MISCREG_HPMCOUNTER07}},
 456     {CSR_HPMCOUNTER08, {"hpmcounter08", MISCREG_HPMCOUNTER08}},
 457     {CSR_HPMCOUNTER09, {"hpmcounter09", MISCREG_HPMCOUNTER09}},
 458     {CSR_HPMCOUNTER10, {"hpmcounter10", MISCREG_HPMCOUNTER10}},
 459     {CSR_HPMCOUNTER11, {"hpmcounter11", MISCREG_HPMCOUNTER11}},
 460     {CSR_HPMCOUNTER12, {"hpmcounter12", MISCREG_HPMCOUNTER12}},
 461     {CSR_HPMCOUNTER13, {"hpmcounter13", MISCREG_HPMCOUNTER13}},
 462     {CSR_HPMCOUNTER14, {"hpmcounter14", MISCREG_HPMCOUNTER14}},
 463     {CSR_HPMCOUNTER15, {"hpmcounter15", MISCREG_HPMCOUNTER15}},
 464     {CSR_HPMCOUNTER16, {"hpmcounter16", MISCREG_HPMCOUNTER16}},
 465     {CSR_HPMCOUNTER17, {"hpmcounter17", MISCREG_HPMCOUNTER17}},
 466     {CSR_HPMCOUNTER18, {"hpmcounter18", MISCREG_HPMCOUNTER18}},
 467     {CSR_HPMCOUNTER19, {"hpmcounter19", MISCREG_HPMCOUNTER19}},
 468     {CSR_HPMCOUNTER20, {"hpmcounter20", MISCREG_HPMCOUNTER20}},
 469     {CSR_HPMCOUNTER21, {"hpmcounter21", MISCREG_HPMCOUNTER21}},
 470     {CSR_HPMCOUNTER22, {"hpmcounter22", MISCREG_HPMCOUNTER22}},
 471     {CSR_HPMCOUNTER23, {"hpmcounter23", MISCREG_HPMCOUNTER23}},
 472     {CSR_HPMCOUNTER24, {"hpmcounter24", MISCREG_HPMCOUNTER24}},
 473     {CSR_HPMCOUNTER25, {"hpmcounter25", MISCREG_HPMCOUNTER25}},
 474     {CSR_HPMCOUNTER26, {"hpmcounter26", MISCREG_HPMCOUNTER26}},
 475     {CSR_HPMCOUNTER27, {"hpmcounter27", MISCREG_HPMCOUNTER27}},
 476     {CSR_HPMCOUNTER28, {"hpmcounter28", MISCREG_HPMCOUNTER28}},
 477     {CSR_HPMCOUNTER29, {"hpmcounter29", MISCREG_HPMCOUNTER29}},
 478     {CSR_HPMCOUNTER30, {"hpmcounter30", MISCREG_HPMCOUNTER30}},
 479     {CSR_HPMCOUNTER31, {"hpmcounter31", MISCREG_HPMCOUNTER31}},
 480
 481     {CSR_SSTATUS, {"sstatus", MISCREG_STATUS}},
 482     {CSR_SEDELEG, {"sedeleg", MISCREG_SEDELEG}},
 483     {CSR_SIDELEG, {"sideleg", MISCREG_SIDELEG}},
 484     {CSR_SIE, {"sie", MISCREG_IE}},
 485     {CSR_STVEC, {"stvec", MISCREG_STVEC}},
 486     {CSR_SSCRATCH, {"sscratch", MISCREG_SSCRATCH}},
 487     {CSR_SEPC, {"sepc", MISCREG_SEPC}},
 488     {CSR_SCAUSE, {"scause", MISCREG_SCAUSE}},
 489     {CSR_STVAL, {"stval", MISCREG_STVAL}},
 490     {CSR_SIP, {"sip", MISCREG_IP}},
 491     {CSR_SATP, {"satp", MISCREG_SATP}},
 492
 493     {CSR_MVENDORID, {"mvendorid", MISCREG_VENDORID}},
 494     {CSR_MARCHID, {"marchid", MISCREG_ARCHID}},
 495     {CSR_MIMPID, {"mimpid", MISCREG_IMPID}},
 496     {CSR_MHARTID, {"mhartid", MISCREG_HARTID}},
 497     {CSR_MSTATUS, {"mstatus", MISCREG_STATUS}},
 498     {CSR_MISA, {"misa", MISCREG_ISA}},
 499     {CSR_MEDELEG, {"medeleg", MISCREG_MEDELEG}},
 500     {CSR_MIDELEG, {"mideleg", MISCREG_MIDELEG}},
 501     {CSR_MIE, {"mie", MISCREG_IE}},
 502     {CSR_MTVEC, {"mtvec", MISCREG_MTVEC}},
 503     {CSR_MSCRATCH, {"mscratch", MISCREG_MSCRATCH}},
 504     {CSR_MEPC, {"mepc", MISCREG_MEPC}},
 505     {CSR_MCAUSE, {"mcause", MISCREG_MCAUSE}},
 506     {CSR_MTVAL, {"mtval", MISCREG_MTVAL}},
 507     {CSR_MIP, {"mip", MISCREG_IP}},
 508     {CSR_PMPCFG0, {"pmpcfg0", MISCREG_PMPCFG0}},
 509     // pmpcfg1 rv32 only
 510     {CSR_PMPCFG2, {"pmpcfg2", MISCREG_PMPCFG2}},
 511     // pmpcfg3 rv32 only
 512     {CSR_PMPADDR00, {"pmpaddr0", MISCREG_PMPADDR00}},
 513     {CSR_PMPADDR01, {"pmpaddr1", MISCREG_PMPADDR01}},
 514     {CSR_PMPADDR02, {"pmpaddr2", MISCREG_PMPADDR02}},
 515     {CSR_PMPADDR03, {"pmpaddr3", MISCREG_PMPADDR03}},
 516     {CSR_PMPADDR04, {"pmpaddr4", MISCREG_PMPADDR04}},
 517     {CSR_PMPADDR05, {"pmpaddr5", MISCREG_PMPADDR05}},
 518     {CSR_PMPADDR06, {"pmpaddr6", MISCREG_PMPADDR06}},
 519     {CSR_PMPADDR07, {"pmpaddr7", MISCREG_PMPADDR07}},
 520     {CSR_PMPADDR08, {"pmpaddr8", MISCREG_PMPADDR08}},
 521     {CSR_PMPADDR09, {"pmpaddr9", MISCREG_PMPADDR09}},
 522     {CSR_PMPADDR10, {"pmpaddr10", MISCREG_PMPADDR10}},
 523     {CSR_PMPADDR11, {"pmpaddr11", MISCREG_PMPADDR11}},
 524     {CSR_PMPADDR12, {"pmpaddr12", MISCREG_PMPADDR12}},
 525     {CSR_PMPADDR13, {"pmpaddr13", MISCREG_PMPADDR13}},
 526     {CSR_PMPADDR14, {"pmpaddr14", MISCREG_PMPADDR14}},
 527     {CSR_PMPADDR15, {"pmpaddr15", MISCREG_PMPADDR15}},
 528     {CSR_MCYCLE, {"mcycle", MISCREG_CYCLE}},
 529     {CSR_MINSTRET, {"minstret", MISCREG_INSTRET}},
 530     {CSR_MHPMCOUNTER03, {"mhpmcounter03", MISCREG_HPMCOUNTER03}},
 531     {CSR_MHPMCOUNTER04, {"mhpmcounter04", MISCREG_HPMCOUNTER04}},
 532     {CSR_MHPMCOUNTER05, {"mhpmcounter05", MISCREG_HPMCOUNTER05}},
 533     {CSR_MHPMCOUNTER06, {"mhpmcounter06", MISCREG_HPMCOUNTER06}},
 534     {CSR_MHPMCOUNTER07, {"mhpmcounter07", MISCREG_HPMCOUNTER07}},
 535     {CSR_MHPMCOUNTER08, {"mhpmcounter08", MISCREG_HPMCOUNTER08}},
 536     {CSR_MHPMCOUNTER09, {"mhpmcounter09", MISCREG_HPMCOUNTER09}},
 537     {CSR_MHPMCOUNTER10, {"mhpmcounter10", MISCREG_HPMCOUNTER10}},
 538     {CSR_MHPMCOUNTER11, {"mhpmcounter11", MISCREG_HPMCOUNTER11}},
 539     {CSR_MHPMCOUNTER12, {"mhpmcounter12", MISCREG_HPMCOUNTER12}},
 540     {CSR_MHPMCOUNTER13, {"mhpmcounter13", MISCREG_HPMCOUNTER13}},
 541     {CSR_MHPMCOUNTER14, {"mhpmcounter14", MISCREG_HPMCOUNTER14}},
 542     {CSR_MHPMCOUNTER15, {"mhpmcounter15", MISCREG_HPMCOUNTER15}},
 543     {CSR_MHPMCOUNTER16, {"mhpmcounter16", MISCREG_HPMCOUNTER16}},
 544     {CSR_MHPMCOUNTER17, {"mhpmcounter17", MISCREG_HPMCOUNTER17}},
 545     {CSR_MHPMCOUNTER18, {"mhpmcounter18", MISCREG_HPMCOUNTER18}},
 546     {CSR_MHPMCOUNTER19, {"mhpmcounter19", MISCREG_HPMCOUNTER19}},
 547     {CSR_MHPMCOUNTER20, {"mhpmcounter20", MISCREG_HPMCOUNTER20}},
 548     {CSR_MHPMCOUNTER21, {"mhpmcounter21", MISCREG_HPMCOUNTER21}},
 549     {CSR_MHPMCOUNTER22, {"mhpmcounter22", MISCREG_HPMCOUNTER22}},
 550     {CSR_MHPMCOUNTER23, {"mhpmcounter23", MISCREG_HPMCOUNTER23}},
 551     {CSR_MHPMCOUNTER24, {"mhpmcounter24", MISCREG_HPMCOUNTER24}},
 552     {CSR_MHPMCOUNTER25, {"mhpmcounter25", MISCREG_HPMCOUNTER25}},
 553     {CSR_MHPMCOUNTER26, {"mhpmcounter26", MISCREG_HPMCOUNTER26}},
 554     {CSR_MHPMCOUNTER27, {"mhpmcounter27", MISCREG_HPMCOUNTER27}},
 555     {CSR_MHPMCOUNTER28, {"mhpmcounter28", MISCREG_HPMCOUNTER28}},
 556     {CSR_MHPMCOUNTER29, {"mhpmcounter29", MISCREG_HPMCOUNTER29}},
 557     {CSR_MHPMCOUNTER30, {"mhpmcounter30", MISCREG_HPMCOUNTER30}},
 558     {CSR_MHPMCOUNTER31, {"mhpmcounter31", MISCREG_HPMCOUNTER31}},
 559     {CSR_MHPMEVENT03, {"mhpmevent03", MISCREG_HPMEVENT03}},
 560     {CSR_MHPMEVENT04, {"mhpmevent04", MISCREG_HPMEVENT04}},
 561     {CSR_MHPMEVENT05, {"mhpmevent05", MISCREG_HPMEVENT05}},
 562     {CSR_MHPMEVENT06, {"mhpmevent06", MISCREG_HPMEVENT06}},
 563     {CSR_MHPMEVENT07, {"mhpmevent07", MISCREG_HPMEVENT07}},
 564     {CSR_MHPMEVENT08, {"mhpmevent08", MISCREG_HPMEVENT08}},
 565     {CSR_MHPMEVENT09, {"mhpmevent09", MISCREG_HPMEVENT09}},
 566     {CSR_MHPMEVENT10, {"mhpmevent10", MISCREG_HPMEVENT10}},
 567     {CSR_MHPMEVENT11, {"mhpmevent11", MISCREG_HPMEVENT11}},
 568     {CSR_MHPMEVENT12, {"mhpmevent12", MISCREG_HPMEVENT12}},
 569     {CSR_MHPMEVENT13, {"mhpmevent13", MISCREG_HPMEVENT13}},
 570     {CSR_MHPMEVENT14, {"mhpmevent14", MISCREG_HPMEVENT14}},
 571     {CSR_MHPMEVENT15, {"mhpmevent15", MISCREG_HPMEVENT15}},
 572     {CSR_MHPMEVENT16, {"mhpmevent16", MISCREG_HPMEVENT16}},
 573     {CSR_MHPMEVENT17, {"mhpmevent17", MISCREG_HPMEVENT17}},
 574     {CSR_MHPMEVENT18, {"mhpmevent18", MISCREG_HPMEVENT18}},
 575     {CSR_MHPMEVENT19, {"mhpmevent19", MISCREG_HPMEVENT19}},
 576     {CSR_MHPMEVENT20, {"mhpmevent20", MISCREG_HPMEVENT20}},
 577     {CSR_MHPMEVENT21, {"mhpmevent21", MISCREG_HPMEVENT21}},
 578     {CSR_MHPMEVENT22, {"mhpmevent22", MISCREG_HPMEVENT22}},
 579     {CSR_MHPMEVENT23, {"mhpmevent23", MISCREG_HPMEVENT23}},
 580     {CSR_MHPMEVENT24, {"mhpmevent24", MISCREG_HPMEVENT24}},
 581     {CSR_MHPMEVENT25, {"mhpmevent25", MISCREG_HPMEVENT25}},
 582     {CSR_MHPMEVENT26, {"mhpmevent26", MISCREG_HPMEVENT26}},
 583     {CSR_MHPMEVENT27, {"mhpmevent27", MISCREG_HPMEVENT27}},
 584     {CSR_MHPMEVENT28, {"mhpmevent28", MISCREG_HPMEVENT28}},
 585     {CSR_MHPMEVENT29, {"mhpmevent29", MISCREG_HPMEVENT29}},
 586     {CSR_MHPMEVENT30, {"mhpmevent30", MISCREG_HPMEVENT30}},
 587     {CSR_MHPMEVENT31, {"mhpmevent31", MISCREG_HPMEVENT31}},
 588
 589     {CSR_TSELECT, {"tselect", MISCREG_TSELECT}},
 590     {CSR_TDATA1, {"tdata1", MISCREG_TDATA1}},
 591     {CSR_TDATA2, {"tdata2", MISCREG_TDATA2}},
 592     {CSR_TDATA3, {"tdata3", MISCREG_TDATA3}},
 593     {CSR_DCSR, {"dcsr", MISCREG_DCSR}},
 594     {CSR_DPC, {"dpc", MISCREG_DPC}},
 595     {CSR_DSCRATCH, {"dscratch", MISCREG_DSCRATCH}}
 596 };
 597
 598 /**
 599  * These fields are specified in the RISC-V Instruction Set Manual, Volume II,
 600  * v1.10, accessible at www.riscv.org. in Figure 3.7. The main register that
 601  * uses these fields is the MSTATUS register, which is shadowed by two others
 602  * accessible at lower privilege levels (SSTATUS and USTATUS) that can't see
 603  * the fields for higher privileges.
 604  */
 605 BitUnion64(STATUS)
 606     Bitfield<63> sd;
 607     Bitfield<35, 34> sxl;
 608     Bitfield<33, 32> uxl;
 609     Bitfield<22> tsr;
 610     Bitfield<21> tw;
 611     Bitfield<20> tvm;
 612     Bitfield<19> mxr;
 613     Bitfield<18> sum;
 614     Bitfield<17> mprv;
 615     Bitfield<16, 15> xs;
 616     Bitfield<14, 13> fs;
 617     Bitfield<12, 11> mpp;
 618     Bitfield<8> spp;
 619     Bitfield<7> mpie;
 620     Bitfield<5> spie;
 621     Bitfield<4> upie;
 622     Bitfield<3> mie;
 623     Bitfield<1> sie;
 624     Bitfield<0> uie;
 625 EndBitUnion(STATUS)
 626
 627 /**
 628  * These fields are specified in the RISC-V Instruction Set Manual, Volume II,
 629  * v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. Both the MIP
 630  * and MIE registers have the same fields, so accesses to either should use
 631  * this bit union.
 632  */
 633 BitUnion64(INTERRUPT)
 634     Bitfield<11> mei;
 635     Bitfield<9> sei;
 636     Bitfield<8> uei;
 637     Bitfield<7> mti;
 638     Bitfield<5> sti;
 639     Bitfield<4> uti;
 640     Bitfield<3> msi;
 641     Bitfield<1> ssi;
 642     Bitfield<0> usi;
 643 EndBitUnion(INTERRUPT)
 644
 645 const off_t MXL_OFFSET = (sizeof(MiscReg) * 8 - 2);
 646 const off_t SXL_OFFSET = 34;
 647 const off_t UXL_OFFSET = 32;
 648 const off_t FS_OFFSET = 13;
 649 const off_t FRM_OFFSET = 5;
 650
 651 const MiscReg ISA_MXL_MASK = 3ULL << MXL_OFFSET;
 652 const MiscReg ISA_EXT_MASK = mask(26);
 653 const MiscReg MISA_MASK = ISA_MXL_MASK | ISA_EXT_MASK;
 654
 655 const MiscReg STATUS_SD_MASK = 1ULL << ((sizeof(MiscReg) * 8) - 1);
 656 const MiscReg STATUS_SXL_MASK = 3ULL << SXL_OFFSET;
 657 const MiscReg STATUS_UXL_MASK = 3ULL << UXL_OFFSET;
 658 const MiscReg STATUS_TSR_MASK = 1ULL << 22;
 659 const MiscReg STATUS_TW_MASK = 1ULL << 21;
 660 const MiscReg STATUS_TVM_MASK = 1ULL << 20;
 661 const MiscReg STATUS_MXR_MASK = 1ULL << 19;
 662 const MiscReg STATUS_SUM_MASK = 1ULL << 18;
 663 const MiscReg STATUS_MPRV_MASK = 1ULL << 17;
 664 const MiscReg STATUS_XS_MASK = 3ULL << 15;
 665 const MiscReg STATUS_FS_MASK = 3ULL << FS_OFFSET;
 666 const MiscReg STATUS_MPP_MASK = 3ULL << 11;
 667 const MiscReg STATUS_SPP_MASK = 1ULL << 8;
 668 const MiscReg STATUS_MPIE_MASK = 1ULL << 7;
 669 const MiscReg STATUS_SPIE_MASK = 1ULL << 5;
 670 const MiscReg STATUS_UPIE_MASK = 1ULL << 4;
 671 const MiscReg STATUS_MIE_MASK = 1ULL << 3;
 672 const MiscReg STATUS_SIE_MASK = 1ULL << 1;
 673 const MiscReg STATUS_UIE_MASK = 1ULL << 0;
 674 const MiscReg MSTATUS_MASK = STATUS_SD_MASK | STATUS_SXL_MASK |
 675                              STATUS_UXL_MASK | STATUS_TSR_MASK |
 676                              STATUS_TW_MASK | STATUS_TVM_MASK |
 677                              STATUS_MXR_MASK | STATUS_SUM_MASK |
 678                              STATUS_MPRV_MASK | STATUS_XS_MASK |
 679                              STATUS_FS_MASK | STATUS_MPP_MASK |
 680                              STATUS_SPP_MASK | STATUS_MPIE_MASK |
 681                              STATUS_SPIE_MASK | STATUS_UPIE_MASK |
 682                              STATUS_MIE_MASK | STATUS_SIE_MASK |
 683                              STATUS_UIE_MASK;
 684 const MiscReg SSTATUS_MASK = STATUS_SD_MASK | STATUS_UXL_MASK |
 685                              STATUS_MXR_MASK | STATUS_SUM_MASK |
 686                              STATUS_XS_MASK | STATUS_FS_MASK |
 687                              STATUS_SPP_MASK | STATUS_SPIE_MASK |
 688                              STATUS_UPIE_MASK | STATUS_SIE_MASK |
 689                              STATUS_UIE_MASK;
 690 const MiscReg USTATUS_MASK = STATUS_SD_MASK | STATUS_MXR_MASK |
 691                              STATUS_SUM_MASK | STATUS_XS_MASK |
 692                              STATUS_FS_MASK | STATUS_UPIE_MASK |
 693                              STATUS_UIE_MASK;
 694
 695 const MiscReg MEI_MASK = 1ULL << 11;
 696 const MiscReg SEI_MASK = 1ULL << 9;
 697 const MiscReg UEI_MASK = 1ULL << 8;
 698 const MiscReg MTI_MASK = 1ULL << 7;
 699 const MiscReg STI_MASK = 1ULL << 5;
 700 const MiscReg UTI_MASK = 1ULL << 4;
 701 const MiscReg MSI_MASK = 1ULL << 3;
 702 const MiscReg SSI_MASK = 1ULL << 1;
 703 const MiscReg USI_MASK = 1ULL << 0;
 704 const MiscReg MI_MASK = MEI_MASK | SEI_MASK | UEI_MASK |
 705                         MTI_MASK | STI_MASK | UTI_MASK |
 706                         MSI_MASK | SSI_MASK | USI_MASK;
 707 const MiscReg SI_MASK = SEI_MASK | UEI_MASK |
 708                         STI_MASK | UTI_MASK |
 709                         SSI_MASK | USI_MASK;
 710 const MiscReg UI_MASK = UEI_MASK | UTI_MASK | USI_MASK;
 711 const MiscReg FFLAGS_MASK = (1 << FRM_OFFSET) - 1;
 712 const MiscReg FRM_MASK = 0x7;
 713
 714 const std::map<int, MiscReg> CSRMasks = {
 715     {CSR_USTATUS, USTATUS_MASK},
 716     {CSR_UIE, UI_MASK},
 717     {CSR_UIP, UI_MASK},
 718     {CSR_FFLAGS, FFLAGS_MASK},
 719     {CSR_FRM, FRM_MASK},
 720     {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)},
 721     {CSR_SSTATUS, SSTATUS_MASK},
 722     {CSR_SIE, SI_MASK},
 723     {CSR_SIP, SI_MASK},
 724     {CSR_MSTATUS, MSTATUS_MASK},
 725     {CSR_MISA, MISA_MASK},
 726     {CSR_MIE, MI_MASK},
 727     {CSR_MIP, MI_MASK}
 728 };
 729
 730 }
 731
 732 #endif // __ARCH_RISCV_REGISTERS_HH__