src/arch/riscv/registers.hh

   1 /*
   2  * Copyright (c) 2013 ARM Limited
   3  * Copyright (c) 2014-2015 Sven Karlsson
   4  * Copyright (c) 2019 Yifei Liu
   5  * Copyright (c) 2020 Barkhausen Institut
   6  * All rights reserved
   7  *
   8  * The license below extends only to copyright in the software and shall
   9  * not be construed as granting a license to any other intellectual
  10  * property including but not limited to intellectual property relating
  11  * to a hardware implementation of the functionality of the software
  12  * licensed hereunder.  You may use the software subject to the license
  13  * terms below provided that you ensure that this notice is replicated
  14  * unmodified and in its entirety in all distributions of the software,
  15  * modified or unmodified, in source code or in binary form.
  16  *
  17  * Copyright (c) 2016 RISC-V Foundation
  18  * Copyright (c) 2016 The University of Virginia
  19  * All rights reserved.
  20  *
  21  * Redistribution and use in source and binary forms, with or without
  22  * modification, are permitted provided that the following conditions are
  23  * met: redistributions of source code must retain the above copyright
  24  * notice, this list of conditions and the following disclaimer;
  25  * redistributions in binary form must reproduce the above copyright
  26  * notice, this list of conditions and the following disclaimer in the
  27  * documentation and/or other materials provided with the distribution;
  28  * neither the name of the copyright holders nor the names of its
  29  * contributors may be used to endorse or promote products derived from
  30  * this software without specific prior written permission.
  31  *
  32  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  33  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  34  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  35  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  36  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  37  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  38  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  39  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  40  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  41  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  42  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  43  */
  44
  45 #ifndef __ARCH_RISCV_REGISTERS_HH__
  46 #define __ARCH_RISCV_REGISTERS_HH__
  47
  48 #include <map>
  49 #include <string>
  50 #include <vector>
  51
  52 #include "arch/generic/types.hh"
  53 #include "arch/generic/vec_pred_reg.hh"
  54 #include "arch/generic/vec_reg.hh"
  55 #include "arch/isa_traits.hh"
  56 #include "arch/riscv/generated/max_inst_regs.hh"
  57 #include "base/types.hh"
  58
  59 namespace RiscvISA {
  60
  61 using RiscvISAInst::MaxInstSrcRegs;
  62 using RiscvISAInst::MaxInstDestRegs;
  63 const int MaxMiscDestRegs = 2;
  64
  65 // Not applicable to RISC-V
  66 using VecElem = ::DummyVecElem;
  67 using VecReg = ::DummyVecReg;
  68 using ConstVecReg = ::DummyConstVecReg;
  69 using VecRegContainer = ::DummyVecRegContainer;
  70 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
  71 constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;
  72
  73 // Not applicable to RISC-V
  74 using VecPredReg = ::DummyVecPredReg;
  75 using ConstVecPredReg = ::DummyConstVecPredReg;
  76 using VecPredRegContainer = ::DummyVecPredRegContainer;
  77 constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
  78 constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
  79
  80 const int NumIntArchRegs = 32;
  81 const int NumMicroIntRegs = 1;
  82 const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs;
  83 const int NumFloatRegs = 32;
  84
  85 const unsigned NumVecRegs = 1;  // Not applicable to RISC-V
  86                                 // (1 to prevent warnings)
  87 const int NumVecPredRegs = 1;  // Not applicable to RISC-V
  88                                // (1 to prevent warnings)
  89
  90 const int NumCCRegs = 0;
  91
  92 // Semantically meaningful register indices
  93 const int ZeroReg = 0;
  94 const int ReturnAddrReg = 1;
  95 const int StackPointerReg = 2;
  96 const int GlobalPointerReg = 3;
  97 const int ThreadPointerReg = 4;
  98 const int FramePointerReg = 8;
  99 const int ReturnValueReg = 10;
 100 const std::vector<int> ReturnValueRegs = {10, 11};
 101 const std::vector<int> ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17};
 102 const int AMOTempReg = 32;
 103
 104 const int SyscallPseudoReturnReg = 10;
 105 const std::vector<int> SyscallArgumentRegs = {10, 11, 12, 13, 14, 15, 16};
 106 const int SyscallNumReg = 17;
 107
 108 const std::vector<std::string> IntRegNames = {
 109     "zero", "ra", "sp", "gp",
 110     "tp", "t0", "t1", "t2",
 111     "s0", "s1", "a0", "a1",
 112     "a2", "a3", "a4", "a5",
 113     "a6", "a7", "s2", "s3",
 114     "s4", "s5", "s6", "s7",
 115     "s8", "s9", "s10", "s11",
 116     "t3", "t4", "t5", "t6"
 117 };
 118 const std::vector<std::string> FloatRegNames = {
 119     "ft0", "ft1", "ft2", "ft3",
 120     "ft4", "ft5", "ft6", "ft7",
 121     "fs0", "fs1", "fa0", "fa1",
 122     "fa2", "fa3", "fa4", "fa5",
 123     "fa6", "fa7", "fs2", "fs3",
 124     "fs4", "fs5", "fs6", "fs7",
 125     "fs8", "fs9", "fs10", "fs11",
 126     "ft8", "ft9", "ft10", "ft11"
 127 };
 128
 129 enum MiscRegIndex {
 130     MISCREG_PRV = 0,
 131     MISCREG_ISA,
 132     MISCREG_VENDORID,
 133     MISCREG_ARCHID,
 134     MISCREG_IMPID,
 135     MISCREG_HARTID,
 136     MISCREG_STATUS,
 137     MISCREG_IP,
 138     MISCREG_IE,
 139     MISCREG_CYCLE,
 140     MISCREG_TIME,
 141     MISCREG_INSTRET,
 142     MISCREG_HPMCOUNTER03,
 143     MISCREG_HPMCOUNTER04,
 144     MISCREG_HPMCOUNTER05,
 145     MISCREG_HPMCOUNTER06,
 146     MISCREG_HPMCOUNTER07,
 147     MISCREG_HPMCOUNTER08,
 148     MISCREG_HPMCOUNTER09,
 149     MISCREG_HPMCOUNTER10,
 150     MISCREG_HPMCOUNTER11,
 151     MISCREG_HPMCOUNTER12,
 152     MISCREG_HPMCOUNTER13,
 153     MISCREG_HPMCOUNTER14,
 154     MISCREG_HPMCOUNTER15,
 155     MISCREG_HPMCOUNTER16,
 156     MISCREG_HPMCOUNTER17,
 157     MISCREG_HPMCOUNTER18,
 158     MISCREG_HPMCOUNTER19,
 159     MISCREG_HPMCOUNTER20,
 160     MISCREG_HPMCOUNTER21,
 161     MISCREG_HPMCOUNTER22,
 162     MISCREG_HPMCOUNTER23,
 163     MISCREG_HPMCOUNTER24,
 164     MISCREG_HPMCOUNTER25,
 165     MISCREG_HPMCOUNTER26,
 166     MISCREG_HPMCOUNTER27,
 167     MISCREG_HPMCOUNTER28,
 168     MISCREG_HPMCOUNTER29,
 169     MISCREG_HPMCOUNTER30,
 170     MISCREG_HPMCOUNTER31,
 171     MISCREG_HPMEVENT03,
 172     MISCREG_HPMEVENT04,
 173     MISCREG_HPMEVENT05,
 174     MISCREG_HPMEVENT06,
 175     MISCREG_HPMEVENT07,
 176     MISCREG_HPMEVENT08,
 177     MISCREG_HPMEVENT09,
 178     MISCREG_HPMEVENT10,
 179     MISCREG_HPMEVENT11,
 180     MISCREG_HPMEVENT12,
 181     MISCREG_HPMEVENT13,
 182     MISCREG_HPMEVENT14,
 183     MISCREG_HPMEVENT15,
 184     MISCREG_HPMEVENT16,
 185     MISCREG_HPMEVENT17,
 186     MISCREG_HPMEVENT18,
 187     MISCREG_HPMEVENT19,
 188     MISCREG_HPMEVENT20,
 189     MISCREG_HPMEVENT21,
 190     MISCREG_HPMEVENT22,
 191     MISCREG_HPMEVENT23,
 192     MISCREG_HPMEVENT24,
 193     MISCREG_HPMEVENT25,
 194     MISCREG_HPMEVENT26,
 195     MISCREG_HPMEVENT27,
 196     MISCREG_HPMEVENT28,
 197     MISCREG_HPMEVENT29,
 198     MISCREG_HPMEVENT30,
 199     MISCREG_HPMEVENT31,
 200     MISCREG_TSELECT,
 201     MISCREG_TDATA1,
 202     MISCREG_TDATA2,
 203     MISCREG_TDATA3,
 204     MISCREG_DCSR,
 205     MISCREG_DPC,
 206     MISCREG_DSCRATCH,
 207
 208     MISCREG_MEDELEG,
 209     MISCREG_MIDELEG,
 210     MISCREG_MTVEC,
 211     MISCREG_MCOUNTEREN,
 212     MISCREG_MSCRATCH,
 213     MISCREG_MEPC,
 214     MISCREG_MCAUSE,
 215     MISCREG_MTVAL,
 216     MISCREG_PMPCFG0,
 217     // pmpcfg1 rv32 only
 218     MISCREG_PMPCFG2,
 219     // pmpcfg3 rv32 only
 220     MISCREG_PMPADDR00,
 221     MISCREG_PMPADDR01,
 222     MISCREG_PMPADDR02,
 223     MISCREG_PMPADDR03,
 224     MISCREG_PMPADDR04,
 225     MISCREG_PMPADDR05,
 226     MISCREG_PMPADDR06,
 227     MISCREG_PMPADDR07,
 228     MISCREG_PMPADDR08,
 229     MISCREG_PMPADDR09,
 230     MISCREG_PMPADDR10,
 231     MISCREG_PMPADDR11,
 232     MISCREG_PMPADDR12,
 233     MISCREG_PMPADDR13,
 234     MISCREG_PMPADDR14,
 235     MISCREG_PMPADDR15,
 236
 237     MISCREG_SEDELEG,
 238     MISCREG_SIDELEG,
 239     MISCREG_STVEC,
 240     MISCREG_SCOUNTEREN,
 241     MISCREG_SSCRATCH,
 242     MISCREG_SEPC,
 243     MISCREG_SCAUSE,
 244     MISCREG_STVAL,
 245     MISCREG_SATP,
 246
 247     MISCREG_UTVEC,
 248     MISCREG_USCRATCH,
 249     MISCREG_UEPC,
 250     MISCREG_UCAUSE,
 251     MISCREG_UTVAL,
 252     MISCREG_FFLAGS,
 253     MISCREG_FRM,
 254
 255     NUM_MISCREGS
 256 };
 257 const int NumMiscRegs = NUM_MISCREGS;
 258
 259 enum CSRIndex {
 260     CSR_USTATUS = 0x000,
 261     CSR_UIE = 0x004,
 262     CSR_UTVEC = 0x005,
 263     CSR_USCRATCH = 0x040,
 264     CSR_UEPC = 0x041,
 265     CSR_UCAUSE = 0x042,
 266     CSR_UTVAL = 0x043,
 267     CSR_UIP = 0x044,
 268     CSR_FFLAGS = 0x001,
 269     CSR_FRM = 0x002,
 270     CSR_FCSR = 0x003,
 271     CSR_CYCLE = 0xC00,
 272     CSR_TIME = 0xC01,
 273     CSR_INSTRET = 0xC02,
 274     CSR_HPMCOUNTER03 = 0xC03,
 275     CSR_HPMCOUNTER04 = 0xC04,
 276     CSR_HPMCOUNTER05 = 0xC05,
 277     CSR_HPMCOUNTER06 = 0xC06,
 278     CSR_HPMCOUNTER07 = 0xC07,
 279     CSR_HPMCOUNTER08 = 0xC08,
 280     CSR_HPMCOUNTER09 = 0xC09,
 281     CSR_HPMCOUNTER10 = 0xC0A,
 282     CSR_HPMCOUNTER11 = 0xC0B,
 283     CSR_HPMCOUNTER12 = 0xC0C,
 284     CSR_HPMCOUNTER13 = 0xC0D,
 285     CSR_HPMCOUNTER14 = 0xC0E,
 286     CSR_HPMCOUNTER15 = 0xC0F,
 287     CSR_HPMCOUNTER16 = 0xC10,
 288     CSR_HPMCOUNTER17 = 0xC11,
 289     CSR_HPMCOUNTER18 = 0xC12,
 290     CSR_HPMCOUNTER19 = 0xC13,
 291     CSR_HPMCOUNTER20 = 0xC14,
 292     CSR_HPMCOUNTER21 = 0xC15,
 293     CSR_HPMCOUNTER22 = 0xC16,
 294     CSR_HPMCOUNTER23 = 0xC17,
 295     CSR_HPMCOUNTER24 = 0xC18,
 296     CSR_HPMCOUNTER25 = 0xC19,
 297     CSR_HPMCOUNTER26 = 0xC1A,
 298     CSR_HPMCOUNTER27 = 0xC1B,
 299     CSR_HPMCOUNTER28 = 0xC1C,
 300     CSR_HPMCOUNTER29 = 0xC1D,
 301     CSR_HPMCOUNTER30 = 0xC1E,
 302     CSR_HPMCOUNTER31 = 0xC1F,
 303     // HPMCOUNTERH rv32 only
 304
 305     CSR_SSTATUS = 0x100,
 306     CSR_SEDELEG = 0x102,
 307     CSR_SIDELEG = 0x103,
 308     CSR_SIE = 0x104,
 309     CSR_STVEC = 0x105,
 310     CSR_SCOUNTEREN = 0x106,
 311     CSR_SSCRATCH = 0x140,
 312     CSR_SEPC = 0x141,
 313     CSR_SCAUSE = 0x142,
 314     CSR_STVAL = 0x143,
 315     CSR_SIP = 0x144,
 316     CSR_SATP = 0x180,
 317
 318     CSR_MVENDORID = 0xF11,
 319     CSR_MARCHID = 0xF12,
 320     CSR_MIMPID = 0xF13,
 321     CSR_MHARTID = 0xF14,
 322     CSR_MSTATUS = 0x300,
 323     CSR_MISA = 0x301,
 324     CSR_MEDELEG = 0x302,
 325     CSR_MIDELEG = 0x303,
 326     CSR_MIE = 0x304,
 327     CSR_MTVEC = 0x305,
 328     CSR_MCOUNTEREN = 0x306,
 329     CSR_MSCRATCH = 0x340,
 330     CSR_MEPC = 0x341,
 331     CSR_MCAUSE = 0x342,
 332     CSR_MTVAL = 0x343,
 333     CSR_MIP = 0x344,
 334     CSR_PMPCFG0 = 0x3A0,
 335     // pmpcfg1 rv32 only
 336     CSR_PMPCFG2 = 0x3A2,
 337     // pmpcfg3 rv32 only
 338     CSR_PMPADDR00 = 0x3B0,
 339     CSR_PMPADDR01 = 0x3B1,
 340     CSR_PMPADDR02 = 0x3B2,
 341     CSR_PMPADDR03 = 0x3B3,
 342     CSR_PMPADDR04 = 0x3B4,
 343     CSR_PMPADDR05 = 0x3B5,
 344     CSR_PMPADDR06 = 0x3B6,
 345     CSR_PMPADDR07 = 0x3B7,
 346     CSR_PMPADDR08 = 0x3B8,
 347     CSR_PMPADDR09 = 0x3B9,
 348     CSR_PMPADDR10 = 0x3BA,
 349     CSR_PMPADDR11 = 0x3BB,
 350     CSR_PMPADDR12 = 0x3BC,
 351     CSR_PMPADDR13 = 0x3BD,
 352     CSR_PMPADDR14 = 0x3BE,
 353     CSR_PMPADDR15 = 0x3BF,
 354     CSR_MCYCLE = 0xB00,
 355     CSR_MINSTRET = 0xB02,
 356     CSR_MHPMCOUNTER03 = 0xC03,
 357     CSR_MHPMCOUNTER04 = 0xC04,
 358     CSR_MHPMCOUNTER05 = 0xC05,
 359     CSR_MHPMCOUNTER06 = 0xC06,
 360     CSR_MHPMCOUNTER07 = 0xC07,
 361     CSR_MHPMCOUNTER08 = 0xC08,
 362     CSR_MHPMCOUNTER09 = 0xC09,
 363     CSR_MHPMCOUNTER10 = 0xC0A,
 364     CSR_MHPMCOUNTER11 = 0xC0B,
 365     CSR_MHPMCOUNTER12 = 0xC0C,
 366     CSR_MHPMCOUNTER13 = 0xC0D,
 367     CSR_MHPMCOUNTER14 = 0xC0E,
 368     CSR_MHPMCOUNTER15 = 0xC0F,
 369     CSR_MHPMCOUNTER16 = 0xC10,
 370     CSR_MHPMCOUNTER17 = 0xC11,
 371     CSR_MHPMCOUNTER18 = 0xC12,
 372     CSR_MHPMCOUNTER19 = 0xC13,
 373     CSR_MHPMCOUNTER20 = 0xC14,
 374     CSR_MHPMCOUNTER21 = 0xC15,
 375     CSR_MHPMCOUNTER22 = 0xC16,
 376     CSR_MHPMCOUNTER23 = 0xC17,
 377     CSR_MHPMCOUNTER24 = 0xC18,
 378     CSR_MHPMCOUNTER25 = 0xC19,
 379     CSR_MHPMCOUNTER26 = 0xC1A,
 380     CSR_MHPMCOUNTER27 = 0xC1B,
 381     CSR_MHPMCOUNTER28 = 0xC1C,
 382     CSR_MHPMCOUNTER29 = 0xC1D,
 383     CSR_MHPMCOUNTER30 = 0xC1E,
 384     CSR_MHPMCOUNTER31 = 0xC1F,
 385     // MHPMCOUNTERH rv32 only
 386     CSR_MHPMEVENT03 = 0x323,
 387     CSR_MHPMEVENT04 = 0x324,
 388     CSR_MHPMEVENT05 = 0x325,
 389     CSR_MHPMEVENT06 = 0x326,
 390     CSR_MHPMEVENT07 = 0x327,
 391     CSR_MHPMEVENT08 = 0x328,
 392     CSR_MHPMEVENT09 = 0x329,
 393     CSR_MHPMEVENT10 = 0x32A,
 394     CSR_MHPMEVENT11 = 0x32B,
 395     CSR_MHPMEVENT12 = 0x32C,
 396     CSR_MHPMEVENT13 = 0x32D,
 397     CSR_MHPMEVENT14 = 0x32E,
 398     CSR_MHPMEVENT15 = 0x32F,
 399     CSR_MHPMEVENT16 = 0x330,
 400     CSR_MHPMEVENT17 = 0x331,
 401     CSR_MHPMEVENT18 = 0x332,
 402     CSR_MHPMEVENT19 = 0x333,
 403     CSR_MHPMEVENT20 = 0x334,
 404     CSR_MHPMEVENT21 = 0x335,
 405     CSR_MHPMEVENT22 = 0x336,
 406     CSR_MHPMEVENT23 = 0x337,
 407     CSR_MHPMEVENT24 = 0x338,
 408     CSR_MHPMEVENT25 = 0x339,
 409     CSR_MHPMEVENT26 = 0x33A,
 410     CSR_MHPMEVENT27 = 0x33B,
 411     CSR_MHPMEVENT28 = 0x33C,
 412     CSR_MHPMEVENT29 = 0x33D,
 413     CSR_MHPMEVENT30 = 0x33E,
 414     CSR_MHPMEVENT31 = 0x33F,
 415
 416     CSR_TSELECT = 0x7A0,
 417     CSR_TDATA1 = 0x7A1,
 418     CSR_TDATA2 = 0x7A2,
 419     CSR_TDATA3 = 0x7A3,
 420     CSR_DCSR = 0x7B0,
 421     CSR_DPC = 0x7B1,
 422     CSR_DSCRATCH = 0x7B2
 423 };
 424
 425 struct CSRMetadata
 426 {
 427     const std::string name;
 428     const int physIndex;
 429 };
 430
 431 const std::map<int, CSRMetadata> CSRData = {
 432     {CSR_USTATUS, {"ustatus", MISCREG_STATUS}},
 433     {CSR_UIE, {"uie", MISCREG_IE}},
 434     {CSR_UTVEC, {"utvec", MISCREG_UTVEC}},
 435     {CSR_USCRATCH, {"uscratch", MISCREG_USCRATCH}},
 436     {CSR_UEPC, {"uepc", MISCREG_UEPC}},
 437     {CSR_UCAUSE, {"ucause", MISCREG_UCAUSE}},
 438     {CSR_UTVAL, {"utval", MISCREG_UTVAL}},
 439     {CSR_UIP, {"uip", MISCREG_IP}},
 440     {CSR_FFLAGS, {"fflags", MISCREG_FFLAGS}},
 441     {CSR_FRM, {"frm", MISCREG_FRM}},
 442     {CSR_FCSR, {"fcsr", MISCREG_FFLAGS}}, // Actually FRM << 5 | FFLAGS
 443     {CSR_CYCLE, {"cycle", MISCREG_CYCLE}},
 444     {CSR_TIME, {"time", MISCREG_TIME}},
 445     {CSR_INSTRET, {"instret", MISCREG_INSTRET}},
 446     {CSR_HPMCOUNTER03, {"hpmcounter03", MISCREG_HPMCOUNTER03}},
 447     {CSR_HPMCOUNTER04, {"hpmcounter04", MISCREG_HPMCOUNTER04}},
 448     {CSR_HPMCOUNTER05, {"hpmcounter05", MISCREG_HPMCOUNTER05}},
 449     {CSR_HPMCOUNTER06, {"hpmcounter06", MISCREG_HPMCOUNTER06}},
 450     {CSR_HPMCOUNTER07, {"hpmcounter07", MISCREG_HPMCOUNTER07}},
 451     {CSR_HPMCOUNTER08, {"hpmcounter08", MISCREG_HPMCOUNTER08}},
 452     {CSR_HPMCOUNTER09, {"hpmcounter09", MISCREG_HPMCOUNTER09}},
 453     {CSR_HPMCOUNTER10, {"hpmcounter10", MISCREG_HPMCOUNTER10}},
 454     {CSR_HPMCOUNTER11, {"hpmcounter11", MISCREG_HPMCOUNTER11}},
 455     {CSR_HPMCOUNTER12, {"hpmcounter12", MISCREG_HPMCOUNTER12}},
 456     {CSR_HPMCOUNTER13, {"hpmcounter13", MISCREG_HPMCOUNTER13}},
 457     {CSR_HPMCOUNTER14, {"hpmcounter14", MISCREG_HPMCOUNTER14}},
 458     {CSR_HPMCOUNTER15, {"hpmcounter15", MISCREG_HPMCOUNTER15}},
 459     {CSR_HPMCOUNTER16, {"hpmcounter16", MISCREG_HPMCOUNTER16}},
 460     {CSR_HPMCOUNTER17, {"hpmcounter17", MISCREG_HPMCOUNTER17}},
 461     {CSR_HPMCOUNTER18, {"hpmcounter18", MISCREG_HPMCOUNTER18}},
 462     {CSR_HPMCOUNTER19, {"hpmcounter19", MISCREG_HPMCOUNTER19}},
 463     {CSR_HPMCOUNTER20, {"hpmcounter20", MISCREG_HPMCOUNTER20}},
 464     {CSR_HPMCOUNTER21, {"hpmcounter21", MISCREG_HPMCOUNTER21}},
 465     {CSR_HPMCOUNTER22, {"hpmcounter22", MISCREG_HPMCOUNTER22}},
 466     {CSR_HPMCOUNTER23, {"hpmcounter23", MISCREG_HPMCOUNTER23}},
 467     {CSR_HPMCOUNTER24, {"hpmcounter24", MISCREG_HPMCOUNTER24}},
 468     {CSR_HPMCOUNTER25, {"hpmcounter25", MISCREG_HPMCOUNTER25}},
 469     {CSR_HPMCOUNTER26, {"hpmcounter26", MISCREG_HPMCOUNTER26}},
 470     {CSR_HPMCOUNTER27, {"hpmcounter27", MISCREG_HPMCOUNTER27}},
 471     {CSR_HPMCOUNTER28, {"hpmcounter28", MISCREG_HPMCOUNTER28}},
 472     {CSR_HPMCOUNTER29, {"hpmcounter29", MISCREG_HPMCOUNTER29}},
 473     {CSR_HPMCOUNTER30, {"hpmcounter30", MISCREG_HPMCOUNTER30}},
 474     {CSR_HPMCOUNTER31, {"hpmcounter31", MISCREG_HPMCOUNTER31}},
 475
 476     {CSR_SSTATUS, {"sstatus", MISCREG_STATUS}},
 477     {CSR_SEDELEG, {"sedeleg", MISCREG_SEDELEG}},
 478     {CSR_SIDELEG, {"sideleg", MISCREG_SIDELEG}},
 479     {CSR_SIE, {"sie", MISCREG_IE}},
 480     {CSR_STVEC, {"stvec", MISCREG_STVEC}},
 481     {CSR_SCOUNTEREN, {"scounteren", MISCREG_SCOUNTEREN}},
 482     {CSR_SSCRATCH, {"sscratch", MISCREG_SSCRATCH}},
 483     {CSR_SEPC, {"sepc", MISCREG_SEPC}},
 484     {CSR_SCAUSE, {"scause", MISCREG_SCAUSE}},
 485     {CSR_STVAL, {"stval", MISCREG_STVAL}},
 486     {CSR_SIP, {"sip", MISCREG_IP}},
 487     {CSR_SATP, {"satp", MISCREG_SATP}},
 488
 489     {CSR_MVENDORID, {"mvendorid", MISCREG_VENDORID}},
 490     {CSR_MARCHID, {"marchid", MISCREG_ARCHID}},
 491     {CSR_MIMPID, {"mimpid", MISCREG_IMPID}},
 492     {CSR_MHARTID, {"mhartid", MISCREG_HARTID}},
 493     {CSR_MSTATUS, {"mstatus", MISCREG_STATUS}},
 494     {CSR_MISA, {"misa", MISCREG_ISA}},
 495     {CSR_MEDELEG, {"medeleg", MISCREG_MEDELEG}},
 496     {CSR_MIDELEG, {"mideleg", MISCREG_MIDELEG}},
 497     {CSR_MIE, {"mie", MISCREG_IE}},
 498     {CSR_MTVEC, {"mtvec", MISCREG_MTVEC}},
 499     {CSR_MCOUNTEREN, {"mcounteren", MISCREG_MCOUNTEREN}},
 500     {CSR_MSCRATCH, {"mscratch", MISCREG_MSCRATCH}},
 501     {CSR_MEPC, {"mepc", MISCREG_MEPC}},
 502     {CSR_MCAUSE, {"mcause", MISCREG_MCAUSE}},
 503     {CSR_MTVAL, {"mtval", MISCREG_MTVAL}},
 504     {CSR_MIP, {"mip", MISCREG_IP}},
 505     {CSR_PMPCFG0, {"pmpcfg0", MISCREG_PMPCFG0}},
 506     // pmpcfg1 rv32 only
 507     {CSR_PMPCFG2, {"pmpcfg2", MISCREG_PMPCFG2}},
 508     // pmpcfg3 rv32 only
 509     {CSR_PMPADDR00, {"pmpaddr0", MISCREG_PMPADDR00}},
 510     {CSR_PMPADDR01, {"pmpaddr1", MISCREG_PMPADDR01}},
 511     {CSR_PMPADDR02, {"pmpaddr2", MISCREG_PMPADDR02}},
 512     {CSR_PMPADDR03, {"pmpaddr3", MISCREG_PMPADDR03}},
 513     {CSR_PMPADDR04, {"pmpaddr4", MISCREG_PMPADDR04}},
 514     {CSR_PMPADDR05, {"pmpaddr5", MISCREG_PMPADDR05}},
 515     {CSR_PMPADDR06, {"pmpaddr6", MISCREG_PMPADDR06}},
 516     {CSR_PMPADDR07, {"pmpaddr7", MISCREG_PMPADDR07}},
 517     {CSR_PMPADDR08, {"pmpaddr8", MISCREG_PMPADDR08}},
 518     {CSR_PMPADDR09, {"pmpaddr9", MISCREG_PMPADDR09}},
 519     {CSR_PMPADDR10, {"pmpaddr10", MISCREG_PMPADDR10}},
 520     {CSR_PMPADDR11, {"pmpaddr11", MISCREG_PMPADDR11}},
 521     {CSR_PMPADDR12, {"pmpaddr12", MISCREG_PMPADDR12}},
 522     {CSR_PMPADDR13, {"pmpaddr13", MISCREG_PMPADDR13}},
 523     {CSR_PMPADDR14, {"pmpaddr14", MISCREG_PMPADDR14}},
 524     {CSR_PMPADDR15, {"pmpaddr15", MISCREG_PMPADDR15}},
 525     {CSR_MCYCLE, {"mcycle", MISCREG_CYCLE}},
 526     {CSR_MINSTRET, {"minstret", MISCREG_INSTRET}},
 527     {CSR_MHPMCOUNTER03, {"mhpmcounter03", MISCREG_HPMCOUNTER03}},
 528     {CSR_MHPMCOUNTER04, {"mhpmcounter04", MISCREG_HPMCOUNTER04}},
 529     {CSR_MHPMCOUNTER05, {"mhpmcounter05", MISCREG_HPMCOUNTER05}},
 530     {CSR_MHPMCOUNTER06, {"mhpmcounter06", MISCREG_HPMCOUNTER06}},
 531     {CSR_MHPMCOUNTER07, {"mhpmcounter07", MISCREG_HPMCOUNTER07}},
 532     {CSR_MHPMCOUNTER08, {"mhpmcounter08", MISCREG_HPMCOUNTER08}},
 533     {CSR_MHPMCOUNTER09, {"mhpmcounter09", MISCREG_HPMCOUNTER09}},
 534     {CSR_MHPMCOUNTER10, {"mhpmcounter10", MISCREG_HPMCOUNTER10}},
 535     {CSR_MHPMCOUNTER11, {"mhpmcounter11", MISCREG_HPMCOUNTER11}},
 536     {CSR_MHPMCOUNTER12, {"mhpmcounter12", MISCREG_HPMCOUNTER12}},
 537     {CSR_MHPMCOUNTER13, {"mhpmcounter13", MISCREG_HPMCOUNTER13}},
 538     {CSR_MHPMCOUNTER14, {"mhpmcounter14", MISCREG_HPMCOUNTER14}},
 539     {CSR_MHPMCOUNTER15, {"mhpmcounter15", MISCREG_HPMCOUNTER15}},
 540     {CSR_MHPMCOUNTER16, {"mhpmcounter16", MISCREG_HPMCOUNTER16}},
 541     {CSR_MHPMCOUNTER17, {"mhpmcounter17", MISCREG_HPMCOUNTER17}},
 542     {CSR_MHPMCOUNTER18, {"mhpmcounter18", MISCREG_HPMCOUNTER18}},
 543     {CSR_MHPMCOUNTER19, {"mhpmcounter19", MISCREG_HPMCOUNTER19}},
 544     {CSR_MHPMCOUNTER20, {"mhpmcounter20", MISCREG_HPMCOUNTER20}},
 545     {CSR_MHPMCOUNTER21, {"mhpmcounter21", MISCREG_HPMCOUNTER21}},
 546     {CSR_MHPMCOUNTER22, {"mhpmcounter22", MISCREG_HPMCOUNTER22}},
 547     {CSR_MHPMCOUNTER23, {"mhpmcounter23", MISCREG_HPMCOUNTER23}},
 548     {CSR_MHPMCOUNTER24, {"mhpmcounter24", MISCREG_HPMCOUNTER24}},
 549     {CSR_MHPMCOUNTER25, {"mhpmcounter25", MISCREG_HPMCOUNTER25}},
 550     {CSR_MHPMCOUNTER26, {"mhpmcounter26", MISCREG_HPMCOUNTER26}},
 551     {CSR_MHPMCOUNTER27, {"mhpmcounter27", MISCREG_HPMCOUNTER27}},
 552     {CSR_MHPMCOUNTER28, {"mhpmcounter28", MISCREG_HPMCOUNTER28}},
 553     {CSR_MHPMCOUNTER29, {"mhpmcounter29", MISCREG_HPMCOUNTER29}},
 554     {CSR_MHPMCOUNTER30, {"mhpmcounter30", MISCREG_HPMCOUNTER30}},
 555     {CSR_MHPMCOUNTER31, {"mhpmcounter31", MISCREG_HPMCOUNTER31}},
 556     {CSR_MHPMEVENT03, {"mhpmevent03", MISCREG_HPMEVENT03}},
 557     {CSR_MHPMEVENT04, {"mhpmevent04", MISCREG_HPMEVENT04}},
 558     {CSR_MHPMEVENT05, {"mhpmevent05", MISCREG_HPMEVENT05}},
 559     {CSR_MHPMEVENT06, {"mhpmevent06", MISCREG_HPMEVENT06}},
 560     {CSR_MHPMEVENT07, {"mhpmevent07", MISCREG_HPMEVENT07}},
 561     {CSR_MHPMEVENT08, {"mhpmevent08", MISCREG_HPMEVENT08}},
 562     {CSR_MHPMEVENT09, {"mhpmevent09", MISCREG_HPMEVENT09}},
 563     {CSR_MHPMEVENT10, {"mhpmevent10", MISCREG_HPMEVENT10}},
 564     {CSR_MHPMEVENT11, {"mhpmevent11", MISCREG_HPMEVENT11}},
 565     {CSR_MHPMEVENT12, {"mhpmevent12", MISCREG_HPMEVENT12}},
 566     {CSR_MHPMEVENT13, {"mhpmevent13", MISCREG_HPMEVENT13}},
 567     {CSR_MHPMEVENT14, {"mhpmevent14", MISCREG_HPMEVENT14}},
 568     {CSR_MHPMEVENT15, {"mhpmevent15", MISCREG_HPMEVENT15}},
 569     {CSR_MHPMEVENT16, {"mhpmevent16", MISCREG_HPMEVENT16}},
 570     {CSR_MHPMEVENT17, {"mhpmevent17", MISCREG_HPMEVENT17}},
 571     {CSR_MHPMEVENT18, {"mhpmevent18", MISCREG_HPMEVENT18}},
 572     {CSR_MHPMEVENT19, {"mhpmevent19", MISCREG_HPMEVENT19}},
 573     {CSR_MHPMEVENT20, {"mhpmevent20", MISCREG_HPMEVENT20}},
 574     {CSR_MHPMEVENT21, {"mhpmevent21", MISCREG_HPMEVENT21}},
 575     {CSR_MHPMEVENT22, {"mhpmevent22", MISCREG_HPMEVENT22}},
 576     {CSR_MHPMEVENT23, {"mhpmevent23", MISCREG_HPMEVENT23}},
 577     {CSR_MHPMEVENT24, {"mhpmevent24", MISCREG_HPMEVENT24}},
 578     {CSR_MHPMEVENT25, {"mhpmevent25", MISCREG_HPMEVENT25}},
 579     {CSR_MHPMEVENT26, {"mhpmevent26", MISCREG_HPMEVENT26}},
 580     {CSR_MHPMEVENT27, {"mhpmevent27", MISCREG_HPMEVENT27}},
 581     {CSR_MHPMEVENT28, {"mhpmevent28", MISCREG_HPMEVENT28}},
 582     {CSR_MHPMEVENT29, {"mhpmevent29", MISCREG_HPMEVENT29}},
 583     {CSR_MHPMEVENT30, {"mhpmevent30", MISCREG_HPMEVENT30}},
 584     {CSR_MHPMEVENT31, {"mhpmevent31", MISCREG_HPMEVENT31}},
 585
 586     {CSR_TSELECT, {"tselect", MISCREG_TSELECT}},
 587     {CSR_TDATA1, {"tdata1", MISCREG_TDATA1}},
 588     {CSR_TDATA2, {"tdata2", MISCREG_TDATA2}},
 589     {CSR_TDATA3, {"tdata3", MISCREG_TDATA3}},
 590     {CSR_DCSR, {"dcsr", MISCREG_DCSR}},
 591     {CSR_DPC, {"dpc", MISCREG_DPC}},
 592     {CSR_DSCRATCH, {"dscratch", MISCREG_DSCRATCH}}
 593 };
 594
 595 /**
 596  * These fields are specified in the RISC-V Instruction Set Manual, Volume II,
 597  * v1.10, accessible at www.riscv.org. in Figure 3.7. The main register that
 598  * uses these fields is the MSTATUS register, which is shadowed by two others
 599  * accessible at lower privilege levels (SSTATUS and USTATUS) that can't see
 600  * the fields for higher privileges.
 601  */
 602 BitUnion64(STATUS)
 603     Bitfield<63> sd;
 604     Bitfield<35, 34> sxl;
 605     Bitfield<33, 32> uxl;
 606     Bitfield<22> tsr;
 607     Bitfield<21> tw;
 608     Bitfield<20> tvm;
 609     Bitfield<19> mxr;
 610     Bitfield<18> sum;
 611     Bitfield<17> mprv;
 612     Bitfield<16, 15> xs;
 613     Bitfield<14, 13> fs;
 614     Bitfield<12, 11> mpp;
 615     Bitfield<8> spp;
 616     Bitfield<7> mpie;
 617     Bitfield<5> spie;
 618     Bitfield<4> upie;
 619     Bitfield<3> mie;
 620     Bitfield<1> sie;
 621     Bitfield<0> uie;
 622 EndBitUnion(STATUS)
 623
 624 /**
 625  * These fields are specified in the RISC-V Instruction Set Manual, Volume II,
 626  * v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. Both the MIP
 627  * and MIE registers have the same fields, so accesses to either should use
 628  * this bit union.
 629  */
 630 BitUnion64(INTERRUPT)
 631     Bitfield<11> mei;
 632     Bitfield<9> sei;
 633     Bitfield<8> uei;
 634     Bitfield<7> mti;
 635     Bitfield<5> sti;
 636     Bitfield<4> uti;
 637     Bitfield<3> msi;
 638     Bitfield<1> ssi;
 639     Bitfield<0> usi;
 640 EndBitUnion(INTERRUPT)
 641
 642 const off_t MXL_OFFSET = (sizeof(uint64_t) * 8 - 2);
 643 const off_t SXL_OFFSET = 34;
 644 const off_t UXL_OFFSET = 32;
 645 const off_t FS_OFFSET = 13;
 646 const off_t FRM_OFFSET = 5;
 647
 648 const RegVal ISA_MXL_MASK = 3ULL << MXL_OFFSET;
 649 const RegVal ISA_EXT_MASK = mask(26);
 650 const RegVal ISA_EXT_C_MASK = 1UL << ('c' - 'a');
 651 const RegVal MISA_MASK = ISA_MXL_MASK | ISA_EXT_MASK;
 652
 653 const RegVal STATUS_SD_MASK = 1ULL << ((sizeof(uint64_t) * 8) - 1);
 654 const RegVal STATUS_SXL_MASK = 3ULL << SXL_OFFSET;
 655 const RegVal STATUS_UXL_MASK = 3ULL << UXL_OFFSET;
 656 const RegVal STATUS_TSR_MASK = 1ULL << 22;
 657 const RegVal STATUS_TW_MASK = 1ULL << 21;
 658 const RegVal STATUS_TVM_MASK = 1ULL << 20;
 659 const RegVal STATUS_MXR_MASK = 1ULL << 19;
 660 const RegVal STATUS_SUM_MASK = 1ULL << 18;
 661 const RegVal STATUS_MPRV_MASK = 1ULL << 17;
 662 const RegVal STATUS_XS_MASK = 3ULL << 15;
 663 const RegVal STATUS_FS_MASK = 3ULL << FS_OFFSET;
 664 const RegVal STATUS_MPP_MASK = 3ULL << 11;
 665 const RegVal STATUS_SPP_MASK = 1ULL << 8;
 666 const RegVal STATUS_MPIE_MASK = 1ULL << 7;
 667 const RegVal STATUS_SPIE_MASK = 1ULL << 5;
 668 const RegVal STATUS_UPIE_MASK = 1ULL << 4;
 669 const RegVal STATUS_MIE_MASK = 1ULL << 3;
 670 const RegVal STATUS_SIE_MASK = 1ULL << 1;
 671 const RegVal STATUS_UIE_MASK = 1ULL << 0;
 672 const RegVal MSTATUS_MASK = STATUS_SD_MASK | STATUS_SXL_MASK |
 673                             STATUS_UXL_MASK | STATUS_TSR_MASK |
 674                             STATUS_TW_MASK | STATUS_TVM_MASK |
 675                             STATUS_MXR_MASK | STATUS_SUM_MASK |
 676                             STATUS_MPRV_MASK | STATUS_XS_MASK |
 677                             STATUS_FS_MASK | STATUS_MPP_MASK |
 678                             STATUS_SPP_MASK | STATUS_MPIE_MASK |
 679                             STATUS_SPIE_MASK | STATUS_UPIE_MASK |
 680                             STATUS_MIE_MASK | STATUS_SIE_MASK |
 681                             STATUS_UIE_MASK;
 682 const RegVal SSTATUS_MASK = STATUS_SD_MASK | STATUS_UXL_MASK |
 683                             STATUS_MXR_MASK | STATUS_SUM_MASK |
 684                             STATUS_XS_MASK | STATUS_FS_MASK |
 685                             STATUS_SPP_MASK | STATUS_SPIE_MASK |
 686                             STATUS_UPIE_MASK | STATUS_SIE_MASK |
 687                             STATUS_UIE_MASK;
 688 const RegVal USTATUS_MASK = STATUS_SD_MASK | STATUS_MXR_MASK |
 689                             STATUS_SUM_MASK | STATUS_XS_MASK |
 690                             STATUS_FS_MASK | STATUS_UPIE_MASK |
 691                             STATUS_UIE_MASK;
 692
 693 const RegVal MEI_MASK = 1ULL << 11;
 694 const RegVal SEI_MASK = 1ULL << 9;
 695 const RegVal UEI_MASK = 1ULL << 8;
 696 const RegVal MTI_MASK = 1ULL << 7;
 697 const RegVal STI_MASK = 1ULL << 5;
 698 const RegVal UTI_MASK = 1ULL << 4;
 699 const RegVal MSI_MASK = 1ULL << 3;
 700 const RegVal SSI_MASK = 1ULL << 1;
 701 const RegVal USI_MASK = 1ULL << 0;
 702 const RegVal MI_MASK = MEI_MASK | SEI_MASK | UEI_MASK |
 703                        MTI_MASK | STI_MASK | UTI_MASK |
 704                        MSI_MASK | SSI_MASK | USI_MASK;
 705 const RegVal SI_MASK = SEI_MASK | UEI_MASK |
 706                        STI_MASK | UTI_MASK |
 707                        SSI_MASK | USI_MASK;
 708 const RegVal UI_MASK = UEI_MASK | UTI_MASK | USI_MASK;
 709 const RegVal FFLAGS_MASK = (1 << FRM_OFFSET) - 1;
 710 const RegVal FRM_MASK = 0x7;
 711
 712 const std::map<int, RegVal> CSRMasks = {
 713     {CSR_USTATUS, USTATUS_MASK},
 714     {CSR_UIE, UI_MASK},
 715     {CSR_UIP, UI_MASK},
 716     {CSR_FFLAGS, FFLAGS_MASK},
 717     {CSR_FRM, FRM_MASK},
 718     {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)},
 719     {CSR_SSTATUS, SSTATUS_MASK},
 720     {CSR_SIE, SI_MASK},
 721     {CSR_SIP, SI_MASK},
 722     {CSR_MSTATUS, MSTATUS_MASK},
 723     {CSR_MISA, MISA_MASK},
 724     {CSR_MIE, MI_MASK},
 725     {CSR_MIP, MI_MASK}
 726 };
 727
 728 }
 729
 730 #endif // __ARCH_RISCV_REGISTERS_HH__