src/arch/riscv/registers.hh

   1 /*
   2  * Copyright (c) 2013 ARM Limited
   3  * Copyright (c) 2014-2015 Sven Karlsson
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2016 RISC-V Foundation
  16  * Copyright (c) 2016 The University of Virginia
  17  * All rights reserved.
  18  *
  19  * Redistribution and use in source and binary forms, with or without
  20  * modification, are permitted provided that the following conditions are
  21  * met: redistributions of source code must retain the above copyright
  22  * notice, this list of conditions and the following disclaimer;
  23  * redistributions in binary form must reproduce the above copyright
  24  * notice, this list of conditions and the following disclaimer in the
  25  * documentation and/or other materials provided with the distribution;
  26  * neither the name of the copyright holders nor the names of its
  27  * contributors may be used to endorse or promote products derived from
  28  * this software without specific prior written permission.
  29  *
  30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  31  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  32  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  33  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  34  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  35  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  36  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  37  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  38  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  39  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  40  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  41  *
  42  * Authors: Andreas Hansson
  43  *          Sven Karlsson
  44  *          Alec Roelke
  45  */
  46
  47 #ifndef __ARCH_RISCV_REGISTERS_HH__
  48 #define __ARCH_RISCV_REGISTERS_HH__
  49
  50 #include <map>
  51 #include <string>
  52
  53 #include "arch/isa_traits.hh"
  54 #include "arch/riscv/generated/max_inst_regs.hh"
  55 #include "base/types.hh"
  56
  57 namespace RiscvISA {
  58
  59 using RiscvISAInst::MaxInstSrcRegs;
  60 using RiscvISAInst::MaxInstDestRegs;
  61 const int MaxMiscDestRegs = 1;
  62
  63 typedef uint_fast16_t RegIndex;
  64 typedef uint64_t IntReg;
  65 typedef uint64_t FloatRegBits;
  66 typedef double FloatReg;
  67 typedef uint8_t CCReg; // Not applicable to Riscv
  68 typedef uint64_t MiscReg;
  69
  70 const int NumIntArchRegs = 32;
  71 const int NumMicroIntRegs = 1;
  72 const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs;
  73 const int NumFloatRegs = 32;
  74 const int NumCCRegs = 0;
  75 const int NumMiscRegs = 4096;
  76
  77 // These help enumerate all the registers for dependence tracking.
  78 const int FP_Reg_Base = NumIntRegs;
  79 const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
  80 const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs;
  81 const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
  82
  83 // Semantically meaningful register indices
  84 const int ZeroReg = 0;
  85 const int ReturnAddrReg = 1;
  86 const int StackPointerReg = 2;
  87 const int GlobalPointerReg = 3;
  88 const int ThreadPointerReg = 4;
  89 const int FramePointerReg = 8;
  90 const int ReturnValueRegs[] = {10, 11};
  91 const int ReturnValueReg = ReturnValueRegs[0];
  92 const int ArgumentRegs[] = {10, 11, 12, 13, 14, 15, 16, 17};
  93 const int AMOTempReg = 32;
  94
  95 const char* const RegisterNames[] = {"zero", "ra", "sp", "gp",
  96     "tp", "t0", "t1", "t2",
  97     "s0", "s1", "a0", "a1",
  98     "a2", "a3", "a4", "a5",
  99     "a6", "a7", "s2", "s3",
 100     "s4", "s5", "s6", "s7",
 101     "s8", "s9", "s10", "s11",
 102     "t3", "t4", "t5", "t6"};
 103
 104 const int SyscallNumReg = ArgumentRegs[7];
 105 const int SyscallArgumentRegs[] = {ArgumentRegs[0], ArgumentRegs[1],
 106     ArgumentRegs[2], ArgumentRegs[3]};
 107 const int SyscallPseudoReturnReg = ReturnValueRegs[0];
 108
 109 enum MiscRegIndex {
 110     MISCREG_FFLAGS = 0x001,
 111     MISCREG_FRM = 0x002,
 112     MISCREG_FCSR = 0x003,
 113     MISCREG_CYCLE = 0xC00,
 114     MISCREG_TIME = 0xC01,
 115     MISCREG_INSTRET = 0xC02,
 116     MISCREG_CYCLEH = 0xC80,
 117     MISCREG_TIMEH = 0xC81,
 118     MISCREG_INSTRETH = 0xC82,
 119
 120     MISCREG_SSTATUS = 0x100,
 121     MISCREG_STVEC = 0x101,
 122     MISCREG_SIE = 0x104,
 123     MISCREG_STIMECMP = 0x121,
 124     MISCREG_STIME = 0xD01,
 125     MISCREG_STIMEH = 0xD81,
 126     MISCREG_SSCRATCH = 0x140,
 127     MISCREG_SEPC = 0x141,
 128     MISCREG_SCAUSE = 0xD42,
 129     MISCREG_SBADADDR = 0xD43,
 130     MISCREG_SIP = 0x144,
 131     MISCREG_SPTBR = 0x180,
 132     MISCREG_SASID = 0x181,
 133     MISCREG_CYCLEW = 0x900,
 134     MISCREG_TIMEW = 0x901,
 135     MISCREG_INSTRETW = 0x902,
 136     MISCREG_CYCLEHW = 0x980,
 137     MISCREG_TIMEHW = 0x981,
 138     MISCREG_INSTRETHW = 0x982,
 139
 140     MISCREG_HSTATUS = 0x200,
 141     MISCREG_HTVEC = 0x201,
 142     MISCREG_HTDELEG = 0x202,
 143     MISCREG_HTIMECMP = 0x221,
 144     MISCREG_HTIME = 0xE01,
 145     MISCREG_HTIMEH = 0xE81,
 146     MISCREG_HSCRATCH = 0x240,
 147     MISCREG_HEPC = 0x241,
 148     MISCREG_HCAUSE = 0x242,
 149     MISCREG_HBADADDR = 0x243,
 150     MISCREG_STIMEW = 0xA01,
 151     MISCREG_STIMEHW = 0xA81,
 152
 153     MISCREG_MCPUID = 0xF00,
 154     MISCREG_MIMPID = 0xF01,
 155     MISCREG_MHARTID = 0xF10,
 156     MISCREG_MSTATUS = 0x300,
 157     MISCREG_MTVEC = 0x301,
 158     MISCREG_MTDELEG = 0x302,
 159     MISCREG_MIE = 0x304,
 160     MISCREG_MTIMECMP = 0x321,
 161     MISCREG_MTIME = 0x701,
 162     MISCREG_MTIMEH = 0x741,
 163     MISCREG_MSCRATCH = 0x340,
 164     MISCREG_MEPC = 0x341,
 165     MISCREG_MCAUSE = 0x342,
 166     MISCREG_MBADADDR = 0x343,
 167     MISCREG_MIP = 0x344,
 168     MISCREG_MBASE = 0x380,
 169     MISCREG_MBOUND = 0x381,
 170     MISCREG_MIBASE = 0x382,
 171     MISCREG_MIBOUND = 0x383,
 172     MISCREG_MDBASE = 0x384,
 173     MISCREG_MDBOUND = 0x385,
 174     MISCREG_HTIMEW = 0xB01,
 175     MISCREG_HTIMEHW = 0xB81,
 176     MISCREG_MTOHOST = 0x780,
 177     MISCREG_MFROMHOST = 0x781
 178 };
 179
 180 }
 181
 182 #endif // __ARCH_RISCV_REGISTERS_HH__