75f1820e4c8ef934787ef58673cc50f6bc8b9396
[gem5.git] / src / arch / riscv / remote_gdb.cc
1 /*
2 * Copyright (c) 2021 Huawei International
3 * Copyright 2015 LabWare
4 * Copyright 2014 Google, Inc.
5 * Copyright (c) 2010 ARM Limited
6 * Copyright (c) 2020 Barkhausen Institut
7 * All rights reserved
8 *
9 * The license below extends only to copyright in the software and shall
10 * not be construed as granting a license to any other intellectual
11 * property including but not limited to intellectual property relating
12 * to a hardware implementation of the functionality of the software
13 * licensed hereunder. You may use the software subject to the license
14 * terms below provided that you ensure that this notice is replicated
15 * unmodified and in its entirety in all distributions of the software,
16 * modified or unmodified, in source code or in binary form.
17 *
18 * Copyright (c) 2017 The University of Virginia
19 * Copyright (c) 2002-2005 The Regents of The University of Michigan
20 * All rights reserved.
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are
24 * met: redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer;
26 * redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution;
29 * neither the name of the copyright holders nor the names of its
30 * contributors may be used to endorse or promote products derived from
31 * this software without specific prior written permission.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
34 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
35 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
36 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
37 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
38 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
39 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
40 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
41 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 */
45
46 /*
47 * Copyright (c) 1990, 1993 The Regents of the University of California
48 * All rights reserved
49 *
50 * This software was developed by the Computer Systems Engineering group
51 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
52 * contributed to Berkeley.
53 *
54 * All advertising materials mentioning features or use of this software
55 * must display the following acknowledgement:
56 * This product includes software developed by the University of
57 * California, Lawrence Berkeley Laboratories.
58 *
59 * Redistribution and use in source and binary forms, with or without
60 * modification, are permitted provided that the following conditions
61 * are met:
62 * 1. Redistributions of source code must retain the above copyright
63 * notice, this list of conditions and the following disclaimer.
64 * 2. Redistributions in binary form must reproduce the above copyright
65 * notice, this list of conditions and the following disclaimer in the
66 * documentation and/or other materials provided with the distribution.
67 * 3. All advertising materials mentioning features or use of this software
68 * must display the following acknowledgement:
69 * This product includes software developed by the University of
70 * California, Berkeley and its contributors.
71 * 4. Neither the name of the University nor the names of its contributors
72 * may be used to endorse or promote products derived from this software
73 * without specific prior written permission.
74 *
75 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
76 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
77 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
78 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
79 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
80 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
81 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
82 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
83 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
84 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85 * SUCH DAMAGE.
86 *
87 * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94
88 */
89
90 /*-
91 * Copyright (c) 2001 The NetBSD Foundation, Inc.
92 * All rights reserved.
93 *
94 * This code is derived from software contributed to The NetBSD Foundation
95 * by Jason R. Thorpe.
96 *
97 * Redistribution and use in source and binary forms, with or without
98 * modification, are permitted provided that the following conditions
99 * are met:
100 * 1. Redistributions of source code must retain the above copyright
101 * notice, this list of conditions and the following disclaimer.
102 * 2. Redistributions in binary form must reproduce the above copyright
103 * notice, this list of conditions and the following disclaimer in the
104 * documentation and/or other materials provided with the distribution.
105 * 3. All advertising materials mentioning features or use of this software
106 * must display the following acknowledgement:
107 * This product includes software developed by the NetBSD
108 * Foundation, Inc. and its contributors.
109 * 4. Neither the name of The NetBSD Foundation nor the names of its
110 * contributors may be used to endorse or promote products derived
111 * from this software without specific prior written permission.
112 *
113 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
114 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
115 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
116 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
117 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
118 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
119 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
120 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
121 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
122 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
123 * POSSIBILITY OF SUCH DAMAGE.
124 */
125
126 /*
127 * $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $
128 *
129 * Taken from NetBSD
130 *
131 * "Stub" to allow remote cpu to debug over a serial line using gdb.
132 */
133
134 #include "arch/riscv/remote_gdb.hh"
135
136 #include <string>
137
138 #include "arch/riscv/mmu.hh"
139 #include "arch/riscv/pagetable_walker.hh"
140 #include "arch/riscv/registers.hh"
141 #include "arch/riscv/tlb.hh"
142 #include "blobs/gdb_xml_riscv_cpu.hh"
143 #include "blobs/gdb_xml_riscv_csr.hh"
144 #include "blobs/gdb_xml_riscv_fpu.hh"
145 #include "blobs/gdb_xml_riscv_target.hh"
146 #include "cpu/thread_state.hh"
147 #include "debug/GDBAcc.hh"
148 #include "mem/page_table.hh"
149 #include "sim/full_system.hh"
150
151 using namespace std;
152 using namespace RiscvISA;
153
154 RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc, int _port)
155 : BaseRemoteGDB(_system, tc, _port), regCache(this)
156 {
157 }
158
159 bool
160 RemoteGDB::acc(Addr va, size_t len)
161 {
162 if (FullSystem)
163 {
164 MMU *mmu = static_cast<MMU *>(context()->getMMUPtr());
165 unsigned logBytes;
166 Addr paddr = va;
167
168 PrivilegeMode pmode = mmu->getMemPriv(context(), BaseTLB::Read);
169 SATP satp = context()->readMiscReg(MISCREG_SATP);
170 if (pmode != PrivilegeMode::PRV_M &&
171 satp.mode != AddrXlateMode::BARE) {
172 Walker *walker = mmu->getDataWalker();
173 Fault fault = walker->startFunctional(
174 context(), paddr, logBytes, BaseTLB::Read);
175 if (fault != NoFault)
176 return false;
177 }
178 return true;
179 }
180
181 return context()->getProcessPtr()->pTable->lookup(va) != nullptr;
182 }
183
184 void
185 RemoteGDB::RiscvGdbRegCache::getRegs(ThreadContext *context)
186 {
187 DPRINTF(GDBAcc, "getregs in remotegdb, size %lu\n", size());
188
189 // General registers
190 for (int i = 0; i < NumIntArchRegs; i++)
191 {
192 r.gpr[i] = context->readIntReg(i);
193 }
194 r.pc = context->pcState().pc();
195
196 // Floating point registers
197 for (int i = 0; i < NumFloatRegs; i++)
198 r.fpu[i] = context->readFloatReg(i);
199 r.fflags = context->readMiscRegNoEffect(
200 CSRData.at(CSR_FFLAGS).physIndex) & CSRMasks.at(CSR_FFLAGS);
201 r.frm = context->readMiscRegNoEffect(
202 CSRData.at(CSR_FRM).physIndex) & CSRMasks.at(CSR_FRM);
203 r.fcsr = context->readMiscRegNoEffect(
204 CSRData.at(CSR_FCSR).physIndex) & CSRMasks.at(CSR_FCSR);
205
206 // CSR registers
207 r.cycle = context->readMiscRegNoEffect(
208 CSRData.at(CSR_CYCLE).physIndex);
209 r.time = context->readMiscRegNoEffect(
210 CSRData.at(CSR_TIME).physIndex);
211
212 // U mode CSR
213 r.ustatus = context->readMiscRegNoEffect(
214 CSRData.at(CSR_USTATUS).physIndex) & CSRMasks.at(CSR_USTATUS);
215 r.uie = context->readMiscRegNoEffect(
216 CSRData.at(CSR_UIE).physIndex) & CSRMasks.at(CSR_UIE);
217 r.utvec = context->readMiscRegNoEffect(
218 CSRData.at(CSR_UTVEC).physIndex);
219 r.uscratch = context->readMiscRegNoEffect(
220 CSRData.at(CSR_USCRATCH).physIndex);
221 r.uepc = context->readMiscRegNoEffect(
222 CSRData.at(CSR_UEPC).physIndex);
223 r.ucause = context->readMiscRegNoEffect(
224 CSRData.at(CSR_UCAUSE).physIndex);
225 r.utval = context->readMiscRegNoEffect(
226 CSRData.at(CSR_UTVAL).physIndex);
227 r.uip = context->readMiscRegNoEffect(
228 CSRData.at(CSR_UIP).physIndex) & CSRMasks.at(CSR_UIP);
229
230 // S mode CSR
231 r.sstatus = context->readMiscRegNoEffect(
232 CSRData.at(CSR_SSTATUS).physIndex) & CSRMasks.at(CSR_SSTATUS);
233 r.sedeleg = context->readMiscRegNoEffect(
234 CSRData.at(CSR_SEDELEG).physIndex);
235 r.sideleg = context->readMiscRegNoEffect(
236 CSRData.at(CSR_SIDELEG).physIndex);
237 r.sie = context->readMiscRegNoEffect(
238 CSRData.at(CSR_SIE).physIndex) & CSRMasks.at(CSR_SIE);
239 r.stvec = context->readMiscRegNoEffect(
240 CSRData.at(CSR_STVEC).physIndex);
241 r.scounteren = context->readMiscRegNoEffect(
242 CSRData.at(CSR_SCOUNTEREN).physIndex);
243 r.sscratch = context->readMiscRegNoEffect(
244 CSRData.at(CSR_SSCRATCH).physIndex);
245 r.sepc = context->readMiscRegNoEffect(
246 CSRData.at(CSR_SEPC).physIndex);
247 r.scause = context->readMiscRegNoEffect(
248 CSRData.at(CSR_SCAUSE).physIndex);
249 r.stval = context->readMiscRegNoEffect(
250 CSRData.at(CSR_STVAL).physIndex);
251 r.sip = context->readMiscRegNoEffect(
252 CSRData.at(CSR_SIP).physIndex) & CSRMasks.at(CSR_SIP);
253 r.satp = context->readMiscRegNoEffect(
254 CSRData.at(CSR_SATP).physIndex);
255
256 // M mode CSR
257 r.mvendorid = context->readMiscRegNoEffect(
258 CSRData.at(CSR_MVENDORID).physIndex);
259 r.marchid = context->readMiscRegNoEffect(
260 CSRData.at(CSR_MARCHID).physIndex);
261 r.mimpid = context->readMiscRegNoEffect(
262 CSRData.at(CSR_MIMPID).physIndex);
263 r.mhartid = context->readMiscRegNoEffect(
264 CSRData.at(CSR_MHARTID).physIndex);
265 r.mstatus = context->readMiscRegNoEffect(
266 CSRData.at(CSR_MSTATUS).physIndex) & CSRMasks.at(CSR_MSTATUS);
267 r.misa = context->readMiscRegNoEffect(
268 CSRData.at(CSR_MISA).physIndex) & CSRMasks.at(CSR_MISA);
269 r.medeleg = context->readMiscRegNoEffect(
270 CSRData.at(CSR_MEDELEG).physIndex);
271 r.mideleg = context->readMiscRegNoEffect(
272 CSRData.at(CSR_MIDELEG).physIndex);
273 r.mie = context->readMiscRegNoEffect(
274 CSRData.at(CSR_MIE).physIndex) & CSRMasks.at(CSR_MIE);
275 r.mtvec = context->readMiscRegNoEffect(
276 CSRData.at(CSR_MTVEC).physIndex);
277 r.mcounteren = context->readMiscRegNoEffect(
278 CSRData.at(CSR_MCOUNTEREN).physIndex);
279 r.mscratch = context->readMiscRegNoEffect(
280 CSRData.at(CSR_MSCRATCH).physIndex);
281 r.mepc = context->readMiscRegNoEffect(
282 CSRData.at(CSR_MEPC).physIndex);
283 r.mcause = context->readMiscRegNoEffect(
284 CSRData.at(CSR_MCAUSE).physIndex);
285 r.mtval = context->readMiscRegNoEffect(
286 CSRData.at(CSR_MTVAL).physIndex);
287 r.mip = context->readMiscRegNoEffect(
288 CSRData.at(CSR_MIP).physIndex) & CSRMasks.at(CSR_MIP);
289
290 // H mode CSR (to be implemented)
291 }
292
293 void
294 RemoteGDB::RiscvGdbRegCache::setRegs(ThreadContext *context) const
295 {
296 // NOTE: no error will be reported for attempting to set masked bits.
297 RegVal oldVal;
298 int mask;
299 RegVal newVal;
300
301 DPRINTF(GDBAcc, "setregs in remotegdb \n");
302 for (int i = 0; i < NumIntArchRegs; i++)
303 context->setIntReg(i, r.gpr[i]);
304 context->pcState(r.pc);
305
306 // Floating point registers
307 for (int i = 0; i < NumFloatRegs; i++)
308 context->setFloatReg(i, r.fpu[i]);
309
310 oldVal = context->readMiscRegNoEffect(
311 CSRData.at(CSR_FFLAGS).physIndex);
312 mask = CSRMasks.at(CSR_FFLAGS);
313 newVal = (oldVal & ~mask) | (r.fflags & mask);
314 context->setMiscRegNoEffect(
315 CSRData.at(CSR_FFLAGS).physIndex, newVal);
316
317 oldVal = context->readMiscRegNoEffect(
318 CSRData.at(CSR_FRM).physIndex);
319 mask = CSRMasks.at(CSR_FRM);
320 newVal = (oldVal & ~mask) | (r.frm & mask);
321 context->setMiscRegNoEffect(
322 CSRData.at(CSR_FRM).physIndex, newVal);
323
324 oldVal = context->readMiscRegNoEffect(
325 CSRData.at(CSR_FCSR).physIndex);
326 mask = CSRMasks.at(CSR_FCSR);
327 newVal = (oldVal & ~mask) | (r.fcsr & mask);
328 context->setMiscRegNoEffect(
329 CSRData.at(CSR_FCSR).physIndex, newVal);
330
331 // CSR registers
332 context->setMiscRegNoEffect(
333 CSRData.at(CSR_CYCLE).physIndex, r.cycle);
334 context->setMiscRegNoEffect(
335 CSRData.at(CSR_TIME).physIndex, r.time);
336
337 // U mode CSR
338 oldVal = context->readMiscRegNoEffect(
339 CSRData.at(CSR_USTATUS).physIndex);
340 mask = CSRMasks.at(CSR_USTATUS);
341 newVal = (oldVal & ~mask) | (r.ustatus & mask);
342 context->setMiscRegNoEffect(
343 CSRData.at(CSR_USTATUS).physIndex, newVal);
344 oldVal = context->readMiscRegNoEffect(
345 CSRData.at(CSR_UIE).physIndex);
346 mask = CSRMasks.at(CSR_UIE);
347 newVal = (oldVal & ~mask) | (r.uie & mask);
348 context->setMiscRegNoEffect(
349 CSRData.at(CSR_UIE).physIndex, newVal);
350 context->setMiscRegNoEffect(
351 CSRData.at(CSR_UTVEC).physIndex, r.utvec);
352 context->setMiscRegNoEffect(
353 CSRData.at(CSR_USCRATCH).physIndex, r.uscratch);
354 context->setMiscRegNoEffect(
355 CSRData.at(CSR_UEPC).physIndex, r.uepc);
356 context->setMiscRegNoEffect(
357 CSRData.at(CSR_UCAUSE).physIndex, r.ucause);
358 context->setMiscRegNoEffect(
359 CSRData.at(CSR_UTVAL).physIndex, r.utval);
360 oldVal = context->readMiscRegNoEffect(
361 CSRData.at(CSR_UIP).physIndex);
362 mask = CSRMasks.at(CSR_UIP);
363 newVal = (oldVal & ~mask) | (r.uip & mask);
364 context->setMiscRegNoEffect(
365 CSRData.at(CSR_UIP).physIndex, newVal);
366
367 // S mode CSR
368 oldVal = context->readMiscRegNoEffect(
369 CSRData.at(CSR_SSTATUS).physIndex);
370 mask = CSRMasks.at(CSR_SSTATUS);
371 newVal = (oldVal & ~mask) | (r.sstatus & mask);
372 context->setMiscRegNoEffect(
373 CSRData.at(CSR_SSTATUS).physIndex, newVal);
374 context->setMiscRegNoEffect(
375 CSRData.at(CSR_SEDELEG).physIndex, r.sedeleg);
376 context->setMiscRegNoEffect(
377 CSRData.at(CSR_SIDELEG).physIndex, r.sideleg);
378 oldVal = context->readMiscRegNoEffect(
379 CSRData.at(CSR_SIE).physIndex);
380 mask = CSRMasks.at(CSR_SIE);
381 newVal = (oldVal & ~mask) | (r.sie & mask);
382 context->setMiscRegNoEffect(
383 CSRData.at(CSR_SIE).physIndex, newVal);
384 context->setMiscRegNoEffect(
385 CSRData.at(CSR_STVEC).physIndex, r.stvec);
386 context->setMiscRegNoEffect(
387 CSRData.at(CSR_SCOUNTEREN).physIndex, r.scounteren);
388 context->setMiscRegNoEffect(
389 CSRData.at(CSR_SSCRATCH).physIndex, r.sscratch);
390 context->setMiscRegNoEffect(
391 CSRData.at(CSR_SEPC).physIndex, r.sepc);
392 context->setMiscRegNoEffect(
393 CSRData.at(CSR_SCAUSE).physIndex, r.scause);
394 context->setMiscRegNoEffect(
395 CSRData.at(CSR_STVAL).physIndex, r.stval);
396 oldVal = context->readMiscRegNoEffect(
397 CSRData.at(CSR_SIP).physIndex);
398 mask = CSRMasks.at(CSR_SIP);
399 newVal = (oldVal & ~mask) | (r.sip & mask);
400 context->setMiscRegNoEffect(
401 CSRData.at(CSR_SIP).physIndex, newVal);
402 context->setMiscRegNoEffect(
403 CSRData.at(CSR_SATP).physIndex, r.satp);
404
405 // M mode CSR
406 context->setMiscRegNoEffect(
407 CSRData.at(CSR_MVENDORID).physIndex, r.mvendorid);
408 context->setMiscRegNoEffect(
409 CSRData.at(CSR_MARCHID).physIndex, r.marchid);
410 context->setMiscRegNoEffect(
411 CSRData.at(CSR_MIMPID).physIndex, r.mimpid);
412 context->setMiscRegNoEffect(
413 CSRData.at(CSR_MHARTID).physIndex, r.mhartid);
414 oldVal = context->readMiscRegNoEffect(
415 CSRData.at(CSR_MSTATUS).physIndex);
416 mask = CSRMasks.at(CSR_MSTATUS);
417 newVal = (oldVal & ~mask) | (r.mstatus & mask);
418 context->setMiscRegNoEffect(
419 CSRData.at(CSR_MSTATUS).physIndex, newVal);
420 oldVal = context->readMiscRegNoEffect(
421 CSRData.at(CSR_MISA).physIndex);
422 mask = CSRMasks.at(CSR_MISA);
423 newVal = (oldVal & ~mask) | (r.misa & mask);
424 context->setMiscRegNoEffect(
425 CSRData.at(CSR_MISA).physIndex, newVal);
426 context->setMiscRegNoEffect(
427 CSRData.at(CSR_MEDELEG).physIndex, r.medeleg);
428 context->setMiscRegNoEffect(
429 CSRData.at(CSR_MIDELEG).physIndex, r.mideleg);
430 oldVal = context->readMiscRegNoEffect(
431 CSRData.at(CSR_MIE).physIndex);
432 mask = CSRMasks.at(CSR_MIE);
433 newVal = (oldVal & ~mask) | (r.mie & mask);
434 context->setMiscRegNoEffect(
435 CSRData.at(CSR_MIE).physIndex, newVal);
436 context->setMiscRegNoEffect(
437 CSRData.at(CSR_MTVEC).physIndex, r.mtvec);
438 context->setMiscRegNoEffect(
439 CSRData.at(CSR_MCOUNTEREN).physIndex, r.mcounteren);
440 context->setMiscRegNoEffect(
441 CSRData.at(CSR_MSCRATCH).physIndex, r.mscratch);
442 context->setMiscRegNoEffect(
443 CSRData.at(CSR_MEPC).physIndex, r.mepc);
444 context->setMiscRegNoEffect(
445 CSRData.at(CSR_MCAUSE).physIndex, r.mcause);
446 context->setMiscRegNoEffect(
447 CSRData.at(CSR_MTVAL).physIndex, r.mtval);
448 oldVal = context->readMiscRegNoEffect(
449 CSRData.at(CSR_MIP).physIndex);
450 mask = CSRMasks.at(CSR_MIP);
451 newVal = (oldVal & ~mask) | (r.mip & mask);
452 context->setMiscRegNoEffect(
453 CSRData.at(CSR_MIP).physIndex, newVal);
454
455 // H mode CSR (to be implemented)
456 }
457
458 bool
459 RemoteGDB::getXferFeaturesRead(const std::string &annex, std::string &output)
460 {
461 /**
462 * Blobs e.g. gdb_xml_riscv_target are generated by adding
463 * GdbXml(<xml_file_name>, <blob_name>) to src/arch/riscv/Sconscript.
464 *
465 * Import using #include blobs/<blob_name>.hh
466 */
467 #define GDB_XML(x, s) \
468 { \
469 x, std::string(reinterpret_cast<const char *>(Blobs::s), \
470 Blobs::s##_len) \
471 }
472 static const std::map<std::string, std::string> annexMap{
473 GDB_XML("target.xml", gdb_xml_riscv_target),
474 GDB_XML("riscv-64bit-cpu.xml", gdb_xml_riscv_cpu),
475 GDB_XML("riscv-64bit-fpu.xml", gdb_xml_riscv_fpu),
476 GDB_XML("riscv-64bit-csr.xml", gdb_xml_riscv_csr)};
477 #undef GDB_XML
478 auto it = annexMap.find(annex);
479 if (it == annexMap.end())
480 return false;
481 output = it->second;
482 return true;
483 }
484
485 BaseGdbRegCache *
486 RemoteGDB::gdbRegs()
487 {
488 return &regCache;
489 }