arch: Bump MaxVecRegLenInBytes to 4096
[gem5.git] / src / arch / riscv / stacktrace.hh
1 /*
2 * Copyright (c) 2005 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * Copyright (c) 2009 The University of Edinburgh
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution;
14 * neither the name of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * Authors: Ali Saidi
31 * Stephen Hines
32 * Timothy M. Jones
33 */
34
35 #ifndef __ARCH_RISCV_STACKTRACE_HH__
36 #define __ARCH_RISCV_STACKTRACE_HH__
37
38 #include "base/trace.hh"
39 #include "cpu/static_inst.hh"
40 #include "debug/Stack.hh"
41
42 class ThreadContext;
43 class StackTrace;
44
45 namespace RiscvISA
46 {
47
48 class ProcessInfo
49 {
50 public:
51 ProcessInfo(ThreadContext *_tc);
52
53 Addr task(Addr ksp) const;
54 int pid(Addr ksp) const;
55 std::string name(Addr ksp) const;
56 };
57
58 class StackTrace
59 {
60 private:
61 ThreadContext *tc;
62 std::vector<Addr> stack;
63
64 private:
65 bool isEntry(Addr addr);
66 bool decodePrologue(Addr sp, Addr callpc, Addr func, int &size, Addr &ra);
67 bool decodeSave(MachInst inst, int &reg, int &disp);
68 bool decodeStack(MachInst inst, int &disp);
69
70 void trace(ThreadContext *tc, bool is_call);
71
72 public:
73 StackTrace();
74 StackTrace(ThreadContext *tc, const StaticInstPtr &inst);
75 ~StackTrace();
76
77 void
78 clear()
79 {
80 tc = 0;
81 stack.clear();
82 }
83
84 bool
85 valid() const
86 {
87 return tc != nullptr;
88 }
89
90 bool trace(ThreadContext *tc, const StaticInstPtr &inst);
91
92 public:
93 const std::vector<Addr> &
94 getstack() const
95 {
96 return stack;
97 }
98
99 static const int user = 1;
100 static const int console = 2;
101 static const int unknown = 3;
102
103 #if TRACING_ON
104 private:
105 void dump();
106
107 public:
108 void
109 dprintf()
110 {
111 if (DTRACE(Stack))
112 dump();
113 }
114 #else
115 public:
116 void
117 dprintf()
118 {
119 }
120 #endif
121 };
122
123 inline bool
124 StackTrace::trace(ThreadContext *tc, const StaticInstPtr &inst)
125 {
126 if (!inst->isCall() && !inst->isReturn())
127 return false;
128
129 if (valid())
130 clear();
131
132 trace(tc, !inst->isReturn());
133 return true;
134 }
135
136 } // namespace RiscvISA
137
138 #endif // __ARCH_RISCV_STACKTRACE_HH__