CPU: Create a microcode ROM object in the CPU which is defined by the ISA.
[gem5.git] / src / arch / sparc / SConscript
1 # -*- mode:python -*-
2
3 # Copyright (c) 2004-2005 The Regents of The University of Michigan
4 # All rights reserved.
5 #
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions are
8 # met: redistributions of source code must retain the above copyright
9 # notice, this list of conditions and the following disclaimer;
10 # redistributions in binary form must reproduce the above copyright
11 # notice, this list of conditions and the following disclaimer in the
12 # documentation and/or other materials provided with the distribution;
13 # neither the name of the copyright holders nor the names of its
14 # contributors may be used to endorse or promote products derived from
15 # this software without specific prior written permission.
16 #
17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #
29 # Authors: Gabe Black
30 # Steve Reinhardt
31
32 Import('*')
33
34 if env['TARGET_ISA'] == 'sparc':
35 # Workaround for bug in SCons version > 0.97d20071212
36 # Scons bug id: 2006 M5 Bug id: 308
37 Dir('isa/formats')
38 Dir('isa/formats/mem')
39 Source('asi.cc')
40 Source('faults.cc')
41 Source('floatregfile.cc')
42 Source('intregfile.cc')
43 Source('miscregfile.cc')
44 Source('pagetable.cc')
45 Source('regfile.cc')
46 Source('remote_gdb.cc')
47 Source('tlb.cc')
48 Source('utility.cc')
49
50 SimObject('SparcTLB.py')
51 TraceFlag('Sparc')
52
53 if env['FULL_SYSTEM']:
54 SimObject('SparcSystem.py')
55 SimObject('SparcInterrupts.py')
56
57 Source('interrupts.cc')
58 Source('stacktrace.cc')
59 Source('system.cc')
60 Source('ua2005.cc')
61 Source('vtophys.cc')
62 else:
63 Source('process.cc')
64
65 Source('linux/linux.cc')
66 Source('linux/process.cc')
67 Source('linux/syscalls.cc')
68
69 Source('solaris/process.cc')
70 Source('solaris/solaris.cc')
71
72 # Add in files generated by the ISA description.
73 isa_desc_files = env.ISADesc('isa/main.isa')
74 # Only non-header files need to be compiled.
75 for f in isa_desc_files:
76 if not f.path.endswith('.hh'):
77 Source(f)