Automated merge with ssh://m5sim.org//repo/m5
[gem5.git] / src / arch / sparc / asi.cc
1 /*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Ali Saidi
30 */
31
32 #include "arch/sparc/asi.hh"
33
34 namespace SparcISA
35 {
36 bool AsiIsBlock(ASI asi)
37 {
38 return
39 (asi == ASI_BLK_AIUP) ||
40 (asi == ASI_BLK_AIUS) ||
41 (asi == ASI_BLK_AIUP_L) ||
42 (asi == ASI_BLK_AIUS_L) ||
43 (asi == ASI_BLK_P) ||
44 (asi == ASI_BLK_S) ||
45 (asi == ASI_BLK_PL) ||
46 (asi == ASI_BLK_SL);
47 }
48
49 bool AsiIsPrimary(ASI asi)
50 {
51 return
52 (asi == ASI_AIUP) ||
53 (asi == ASI_BLK_AIUP) ||
54 (asi == ASI_AIUP_L) ||
55 (asi == ASI_BLK_AIUP_L) ||
56 (asi == ASI_LDTX_AIUP) ||
57 (asi == ASI_LDTX_AIUP_L) ||
58 (asi == ASI_P) ||
59 (asi == ASI_PNF) ||
60 (asi == ASI_PL) ||
61 (asi == ASI_PNFL) ||
62 (asi == ASI_PST8_P) ||
63 (asi == ASI_PST16_P) ||
64 (asi == ASI_PST32_P) ||
65 (asi == ASI_PST8_PL) ||
66 (asi == ASI_PST16_PL) ||
67 (asi == ASI_PST32_PL) ||
68 (asi == ASI_FL8_P) ||
69 (asi == ASI_FL16_P) ||
70 (asi == ASI_FL8_PL) ||
71 (asi == ASI_FL16_PL) ||
72 (asi == ASI_LDTX_P) ||
73 (asi == ASI_LDTX_PL) ||
74 (asi == ASI_BLK_P) ||
75 (asi == ASI_BLK_PL);
76 }
77
78 bool AsiIsSecondary(ASI asi)
79 {
80 return
81 (asi == ASI_AIUS) ||
82 (asi == ASI_BLK_AIUS) ||
83 (asi == ASI_AIUS_L) ||
84 (asi == ASI_BLK_AIUS_L) ||
85 (asi == ASI_LDTX_AIUS) ||
86 (asi == ASI_LDTX_AIUS_L) ||
87 (asi == ASI_S) ||
88 (asi == ASI_SNF) ||
89 (asi == ASI_SL) ||
90 (asi == ASI_SNFL) ||
91 (asi == ASI_PST8_S) ||
92 (asi == ASI_PST16_S) ||
93 (asi == ASI_PST32_S) ||
94 (asi == ASI_PST8_SL) ||
95 (asi == ASI_PST16_SL) ||
96 (asi == ASI_PST32_SL) ||
97 (asi == ASI_FL8_S) ||
98 (asi == ASI_FL16_S) ||
99 (asi == ASI_FL8_SL) ||
100 (asi == ASI_FL16_SL) ||
101 (asi == ASI_LDTX_S) ||
102 (asi == ASI_LDTX_SL) ||
103 (asi == ASI_BLK_S) ||
104 (asi == ASI_BLK_SL);
105 }
106
107 bool AsiIsNucleus(ASI asi)
108 {
109 return
110 (asi == ASI_N) ||
111 (asi == ASI_NL) ||
112 (asi == ASI_LDTX_N) ||
113 (asi == ASI_LDTX_NL);
114 }
115
116 bool AsiIsAsIfUser(ASI asi)
117 {
118 return
119 (asi == ASI_AIUP) ||
120 (asi == ASI_AIUS) ||
121 (asi == ASI_BLK_AIUP) ||
122 (asi == ASI_BLK_AIUS) ||
123 (asi == ASI_AIUP_L) ||
124 (asi == ASI_AIUS_L) ||
125 (asi == ASI_BLK_AIUP_L) ||
126 (asi == ASI_BLK_AIUS_L) ||
127 (asi == ASI_LDTX_AIUP) ||
128 (asi == ASI_LDTX_AIUS) ||
129 (asi == ASI_LDTX_AIUP_L) ||
130 (asi == ASI_LDTX_AIUS_L);
131 }
132
133 bool AsiIsIO(ASI asi)
134 {
135 return
136 (asi == ASI_REAL_IO) ||
137 (asi == ASI_REAL_IO_L);
138 }
139
140 bool AsiIsReal(ASI asi)
141 {
142 return
143 (asi == ASI_REAL) ||
144 (asi == ASI_REAL_IO) ||
145 (asi == ASI_REAL_L) ||
146 (asi == ASI_REAL_IO_L) ||
147 (asi == ASI_LDTX_REAL) ||
148 (asi == ASI_LDTX_REAL_L);
149 }
150
151 bool AsiIsLittle(ASI asi)
152 {
153 return
154 (asi == ASI_NL) ||
155 (asi == ASI_AIUP_L) ||
156 (asi == ASI_AIUS_L) ||
157 (asi == ASI_REAL_L) ||
158 (asi == ASI_REAL_IO_L) ||
159 (asi == ASI_BLK_AIUP_L) ||
160 (asi == ASI_BLK_AIUS_L) ||
161 (asi == ASI_LDTX_AIUP_L) ||
162 (asi == ASI_LDTX_AIUS_L) ||
163 (asi == ASI_LDTX_REAL_L) ||
164 (asi == ASI_LDTX_NL) ||
165 (asi == ASI_PL) ||
166 (asi == ASI_SL) ||
167 (asi == ASI_PNFL) ||
168 (asi == ASI_SNFL) ||
169 (asi == ASI_PST8_PL) ||
170 (asi == ASI_PST8_SL) ||
171 (asi == ASI_PST16_PL) ||
172 (asi == ASI_PST16_SL) ||
173 (asi == ASI_PST32_PL) ||
174 (asi == ASI_PST32_SL) ||
175 (asi == ASI_FL8_PL) ||
176 (asi == ASI_FL8_SL) ||
177 (asi == ASI_FL16_PL) ||
178 (asi == ASI_FL16_SL) ||
179 (asi == ASI_LDTX_PL) ||
180 (asi == ASI_LDTX_SL) ||
181 (asi == ASI_BLK_PL) ||
182 (asi == ASI_BLK_SL) ||
183 (asi == ASI_LTX_L);
184 }
185
186 bool AsiIsTwin(ASI asi)
187 {
188 return
189 (asi >= ASI_LDTX_AIUP &&
190 asi <= ASI_LDTX_N &&
191 asi != ASI_QUEUE) ||
192 (asi >= ASI_LDTX_AIUP_L &&
193 asi <= ASI_LDTX_NL &&
194 asi != 0x2D) ||
195 asi == ASI_LDTX_P ||
196 asi == ASI_LDTX_S ||
197 asi == ASI_LDTX_PL ||
198 asi == ASI_LDTX_SL;
199 }
200
201 bool AsiIsPartialStore(ASI asi)
202 {
203 return
204 (asi == ASI_PST8_P) ||
205 (asi == ASI_PST8_S) ||
206 (asi == ASI_PST16_P) ||
207 (asi == ASI_PST16_S) ||
208 (asi == ASI_PST32_P) ||
209 (asi == ASI_PST32_S) ||
210 (asi == ASI_PST8_PL) ||
211 (asi == ASI_PST8_SL) ||
212 (asi == ASI_PST16_PL) ||
213 (asi == ASI_PST16_SL) ||
214 (asi == ASI_PST32_PL) ||
215 (asi == ASI_PST32_SL);
216 }
217
218 bool AsiIsFloatingLoad(ASI asi)
219 {
220 return
221 (asi == ASI_FL8_P) ||
222 (asi == ASI_FL8_S) ||
223 (asi == ASI_FL16_P) ||
224 (asi == ASI_FL16_S) ||
225 (asi == ASI_FL8_PL) ||
226 (asi == ASI_FL8_SL) ||
227 (asi == ASI_FL16_PL) ||
228 (asi == ASI_FL16_SL);
229 }
230
231 bool AsiIsNoFault(ASI asi)
232 {
233 return
234 (asi == ASI_PNF) ||
235 (asi == ASI_SNF) ||
236 (asi == ASI_PNFL) ||
237 (asi == ASI_SNFL);
238 }
239
240 bool AsiIsScratchPad(ASI asi)
241 {
242 return
243 (asi == ASI_SCRATCHPAD) ||
244 (asi == ASI_HYP_SCRATCHPAD);
245 }
246
247 bool AsiIsCmt(ASI asi)
248 {
249 return
250 (asi == ASI_CMT_PER_STRAND) ||
251 (asi == ASI_CMT_SHARED);
252 }
253
254 bool AsiIsQueue(ASI asi)
255 {
256 return asi == ASI_QUEUE;
257 }
258
259 bool AsiIsInterrupt(ASI asi)
260 {
261 return asi == ASI_SWVR_INTR_RECEIVE ||
262 asi == ASI_SWVR_UDB_INTR_W ||
263 asi == ASI_SWVR_UDB_INTR_R ;
264 }
265
266 bool AsiIsMmu(ASI asi)
267 {
268 return asi == ASI_MMU ||
269 asi == ASI_LSU_CONTROL_REG ||
270 (asi >= ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0 &&
271 asi <= ASI_IMMU_CTXT_ZERO_CONFIG) ||
272 (asi >= ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0 &&
273 asi <= ASI_IMMU_CTXT_NONZERO_CONFIG) ||
274 (asi >= ASI_IMMU &&
275 asi <= ASI_IMMU_TSB_PS1_PTR_REG) ||
276 (asi >= ASI_ITLB_DATA_IN_REG &&
277 asi <= ASI_TLB_INVALIDATE_ALL);
278 }
279
280 bool AsiIsUnPriv(ASI asi)
281 {
282 return asi >= 0x80;
283 }
284
285 bool AsiIsPriv(ASI asi)
286 {
287 return asi <= 0x2f;
288 }
289
290
291 bool AsiIsHPriv(ASI asi)
292 {
293 return asi >= 0x30 && asi <= 0x7f;
294 }
295
296 bool AsiIsReg(ASI asi)
297 {
298 return AsiIsMmu(asi) || AsiIsScratchPad(asi) ||
299 AsiIsSparcError(asi) || AsiIsInterrupt(asi)
300 || AsiIsCmt(asi);
301 }
302
303 bool AsiIsSparcError(ASI asi)
304 {
305 return asi == ASI_SPARC_ERROR_EN_REG ||
306 asi == ASI_SPARC_ERROR_STATUS_REG;
307 }
308
309 }