src/arch/sparc/asi.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Ali Saidi
  30  */
  31
  32 #ifndef __ARCH_SPARC_ASI_HH__
  33 #define __ARCH_SPARC_ASI_HH__
  34
  35 namespace SparcISA
  36 {
  37     enum ASI {
  38         ASI_IMPLICIT = 0x00,
  39         /* Priveleged ASIs */
  40         //0x00-0x03 implementation dependent
  41         ASI_NUCLEUS = 0x4,
  42         ASI_N = 0x4,
  43         //0x05-0x0B implementation dependent
  44         ASI_NL = 0xC,
  45         ASI_NUCLEUS_LITTLE = ASI_NL,
  46         //0x0D-0x0F implementation dependent
  47         ASI_AIUP = 0x10,
  48         ASI_AS_IF_USER_PRIMARY = ASI_AIUP,
  49         ASI_AIUS = 0x11,
  50         ASI_AS_IF_USER_SECONDARY = ASI_AIUS,
  51         //0x12-0x13 implementation dependent
  52         ASI_REAL = 0x14,
  53         ASI_REAL_IO = 0x15,
  54         ASI_BLK_AIUP = 0x16,
  55         ASI_BLOCK_AS_IF_USER_PRIMARY = ASI_BLK_AIUP,
  56         ASI_BLK_AIUS = 0x17,
  57         ASI_BLOCK_AS_IF_USER_SECONDARY = ASI_BLK_AIUS,
  58         ASI_AIUP_L = 0x18,
  59         ASI_AS_IF_USER_PRIMARY_LITTLE = ASI_AIUP_L,
  60         ASI_AIUS_L = 0x19,
  61         ASI_AS_IF_USER_SECONDARY_LITTLE = ASI_AIUS_L,
  62         //0x1A-0x1B implementation dependent
  63         ASI_REAL_L = 0x1C,
  64         ASI_REAL_LITTLE = ASI_REAL_L,
  65         ASI_REAL_IO_L = 0x1D,
  66         ASI_REAL_IO_LITTLE = ASI_REAL_IO_L,
  67         ASI_BLK_AIUP_L = 0x1E,
  68         ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE = ASI_BLK_AIUP_L,
  69         ASI_BLK_AIUS_L = 0x1F,
  70         ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE = ASI_BLK_AIUS_L,
  71         ASI_SCRATCHPAD = 0x20,
  72         ASI_MMU = 0x21,
  73         ASI_LDTX_AIUP = 0x22,
  74         ASI_LD_TWINX_AS_IF_USER_PRIMARY = ASI_LDTX_AIUP,
  75         ASI_LDTX_AIUS = 0x23,
  76         ASI_LD_TWINX_AS_IF_USER_SECONDARY = ASI_LDTX_AIUS,
  77         ASI_QUAD_LDD = 0x24,
  78         ASI_QUEUE = 0x25,
  79         ASI_QUAD_LDD_REAL = 0x26,
  80         ASI_LDTX_REAL = ASI_QUAD_LDD_REAL,
  81         ASI_LDTX_N = 0x27,
  82         ASI_LD_TWINX_NUCLEUS = ASI_LDTX_N,
  83         ASI_ST_BLKINIT_NUCLEUS = ASI_LDTX_N,
  84         ASI_STBI_N = ASI_LDTX_N,
  85         //0x28-0x29 implementation dependent
  86         ASI_LDTX_AIUP_L = 0x2A,
  87         ASI_TWINX_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUP_L,
  88         ASI_ST_BLKINIT_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUP_L,
  89         ASI_STBI_AIUP_L = ASI_LDTX_AIUP_L,
  90         ASI_LDTX_AIUS_L = 0x2B,
  91         ASI_LD_TWINX_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUS_L,
  92         ASI_ST_BLKINIT_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUS_L,
  93         ASI_STBI_AIUS_L = ASI_LDTX_AIUS_L,
  94         ASI_LTX_L = 0x2C,
  95         ASI_TWINX_LITTLE = ASI_LTX_L,
  96         //0x2D implementation dependent
  97         ASI_LDTX_REAL_L = 0x2E,
  98         ASI_LD_TWINX_REAL_LITTLE = ASI_LDTX_REAL_L,
  99         ASI_LDTX_NL = 0x2F,
 100         ASI_LD_TWINX_NUCLEUS_LITTLE = ASI_LDTX_NL,
 101         //0x20 implementation dependent
 102         ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x31,
 103         ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x32,
 104         ASI_DMMU_CTXT_ZERO_CONFIG = 0x33,
 105         //0x34 implementation dependent
 106         ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x35,
 107         ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x36,
 108         ASI_IMMU_CTXT_ZERO_CONFIG = 0x37,
 109         //0x38 implementation dependent
 110         ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x39,
 111         ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1 = 0x3A,
 112         ASI_DMMU_CTXT_NONZERO_CONFIG = 0x3B,
 113         //0x3C implementation dependent
 114         ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x3D,
 115         ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1 = 0x3E,
 116         ASI_IMMU_CTXT_NONZERO_CONFIG = 0x3F,
 117         ASI_STREAM_MA = 0x40,
 118         //0x41 implementation dependent
 119         ASI_SPARC_BIST_CONTROL = 0x42,
 120         ASI_INST_MASK_REG = 0x42,
 121         ASI_LSU_DIAG_REG = 0x42,
 122         //0x43 implementation dependent
 123         ASI_STM_CTL_REG = 0x44,
 124         ASI_LSU_CONTROL_REG = 0x45,
 125         ASI_DCACHE_DATA = 0x46,
 126         ASI_DCACHE_TAG = 0x47,
 127         ASI_INTR_DISPATCH_STATUS = 0x48,
 128         ASI_INTR_RECEIVE = 0x49,
 129         ASI_UPA_CONFIG_REGISTER = 0x4A,
 130         ASI_SPARC_ERROR_EN_REG = 0x4B,
 131         ASI_SPARC_ERROR_STATUS_REG = 0x4C,
 132         ASI_SPARC_ERROR_ADDRESS_REG = 0x4D,
 133         ASI_ECACHE_TAG_DATA = 0x4E,
 134         ASI_HYP_SCRATCHPAD = 0x4F,
 135         ASI_IMMU = 0x50,
 136         ASI_IMMU_TSB_PS0_PTR_REG = 0x51,
 137         ASI_IMMU_TSB_PS1_PTR_REG = 0x52,
 138         //0x53 implementation dependent
 139         ASI_ITLB_DATA_IN_REG = 0x54,
 140         ASI_ITLB_DATA_ACCESS_REG = 0x55,
 141         ASI_ITLB_TAG_READ_REG = 0x56,
 142         ASI_IMMU_DEMAP = 0x57,
 143         ASI_DMMU = 0x58,
 144         ASI_DMMU_TSB_PS0_PTR_REG = 0x59,
 145         ASI_DMMU_TSB_PS1_PTR_REG = 0x5A,
 146         ASI_DMMU_TSB_DIRECT_PTR_REG = 0x5B,
 147         ASI_DTLB_DATA_IN_REG = 0x5C,
 148         ASI_DTLB_DATA_ACCESS_REG = 0x5D,
 149         ASI_DTLB_TAG_READ_REG = 0x5E,
 150         ASI_DMMU_DEMAP = 0x5F,
 151         ASI_TLB_INVALIDATE_ALL = 0x60,
 152         //0x61-0x62 implementation dependent
 153         ASI_CMT_PER_STRAND = 0x63,
 154         //0x64-0x65 implementation dependent
 155         ASI_ICACHE_INSTR = 0x66,
 156         ASI_ICACHE_TAG = 0x67,
 157         //0x68-0x71 implementation dependent
 158         ASI_SWVR_INTR_RECEIVE = 0x72,
 159         ASI_SWVR_UDB_INTR_W = 0x73,
 160         ASI_SWVR_UDB_INTR_R = 0x74,
 161         //0x74-0x7F reserved
 162         /* Unpriveleged ASIs */
 163         ASI_P = 0x80,
 164         ASI_PRIMARY = ASI_P,
 165         ASI_S = 0x81,
 166         ASI_SECONDARY = ASI_S,
 167         ASI_PNF = 0x82,
 168         ASI_PRIMARY_NO_FAULT = ASI_PNF,
 169         ASI_SNF = 0x83,
 170         ASI_SECONDARY_NO_FAULT = ASI_SNF,
 171         //0x84-0x87 reserved
 172         ASI_PL = 0x88,
 173         ASI_PRIMARY_LITTLE = ASI_PL,
 174         ASI_SL = 0x89,
 175         ASI_SECONDARY_LITTLE = ASI_SL,
 176         ASI_PNFL = 0x8A,
 177         ASI_PRIMARY_NO_FAULT_LITTLE = ASI_PNFL,
 178         ASI_SNFL = 0x8B,
 179         ASI_SECONDARY_NO_FAULT_LITTLE = ASI_SNFL,
 180         //0x8C-0xBF reserved
 181         ASI_PST8_P = 0xC0,
 182         ASI_PST8_PRIMARY = ASI_PST8_P,
 183         ASI_PST8_S = 0xC1,
 184         ASI_PST8_SECONDARY = ASI_PST8_S,
 185         ASI_PST16_P = 0xC2,
 186         ASI_PST16_PRIMARY = ASI_PST16_P,
 187         ASI_PST16_S = 0xC3,
 188         ASI_PST16_SECONDARY = ASI_PST16_S,
 189         ASI_PST32_P = 0xC4,
 190         ASI_PST32_PRIMARY = ASI_PST32_P,
 191         ASI_PST32_S = 0xC5,
 192         ASI_PST32_SECONDARY = ASI_PST32_S,
 193         //0xC6-0xC7 implementation dependent
 194         ASI_PST8_PL = 0xC8,
 195         ASI_PST8_PRIMARY_LITTLE = ASI_PST8_PL,
 196         ASI_PST8_SL = 0xC9,
 197         ASI_PST8_SECONDARY_LITTLE = ASI_PST8_SL,
 198         ASI_PST16_PL = 0xCA,
 199         ASI_PST16_PRIMARY_LITTLE = ASI_PST16_PL,
 200         ASI_PST16_SL = 0xCB,
 201         ASI_PST16_SECONDARY_LITTLE = ASI_PST16_SL,
 202         ASI_PST32_PL = 0xCC,
 203         ASI_PST32_PRIMARY_LITTLE = ASI_PST32_PL,
 204         ASI_PST32_SL = 0xCD,
 205         ASI_PST32_SECONDARY_LITTLE = ASI_PST32_SL,
 206         //0xCE-0xCF implementation dependent
 207         ASI_FL8_P = 0xD0,
 208         ASI_FL8_PRIMARY = ASI_FL8_P,
 209         ASI_FL8_S = 0xD1,
 210         ASI_FL8_SECONDARY = ASI_FL8_S,
 211         ASI_FL16_P = 0xD2,
 212         ASI_FL16_PRIMARY = ASI_FL16_P,
 213         ASI_FL16_S = 0xD3,
 214         ASI_FL16_SECONDARY = ASI_FL16_S,
 215         //0xD4-0xD7 implementation dependent
 216         ASI_FL8_PL = 0xD8,
 217         ASI_FL8_PRIMARY_LITTLE = ASI_FL8_PL,
 218         ASI_FL8_SL = 0xD9,
 219         ASI_FL8_SECONDARY_LITTLE = ASI_FL8_SL,
 220         ASI_FL16_PL = 0xDA,
 221         ASI_FL16_PRIMARY_LITTLE = ASI_FL16_PL,
 222         ASI_FL16_SL = 0xDB,
 223         ASI_FL16_SECONDARY_LITTLE = ASI_FL16_SL,
 224         //0xDC-0xDF implementation dependent
 225         //0xE0-0xE1 reserved
 226         ASI_LDTX_P = 0xE2,
 227         ASI_LD_TWINX_PRIMARY = ASI_LDTX_P,
 228         ASI_LDTX_S = 0xE3,
 229         ASI_LD_TWINX_SECONDARY = ASI_LDTX_S,
 230         //0xE4-0xE9 implementation dependent
 231         ASI_LDTX_PL = 0xEA,
 232         ASI_LD_TWINX_PRIMARY_LITTLE = ASI_LDTX_PL,
 233         ASI_LDTX_SL = 0xEB,
 234         ASI_LD_TWINX_SECONDARY_LITTLE = ASI_LDTX_SL,
 235         //0xEC-0xEF implementation dependent
 236         ASI_BLK_P = 0xF0,
 237         ASI_BLOCK_PRIMARY = ASI_BLK_P,
 238         ASI_BLK_S = 0xF1,
 239         ASI_BLOCK_SECONDARY = ASI_BLK_S,
 240         //0xF2-0xF7 implementation dependent
 241         ASI_BLK_PL = 0xF8,
 242         ASI_BLOCK_PRIMARY_LITTLE = ASI_BLK_PL,
 243         ASI_BLK_SL = 0xF9,
 244         ASI_BLOCK_SECONDARY_LITTLE = ASI_BLK_SL,
 245         //0xFA-0xFF implementation dependent
 246         MAX_ASI = 0xFF
 247     };
 248
 249     //Functions that classify an asi
 250     bool AsiIsBlock(ASI);
 251     bool AsiIsPrimary(ASI);
 252     bool AsiIsSecondary(ASI);
 253     bool AsiIsNucleus(ASI);
 254     bool AsiIsAsIfUser(ASI);
 255     bool AsiIsIO(ASI);
 256     bool AsiIsReal(ASI);
 257     bool AsiIsLittle(ASI);
 258     bool AsiIsTwin(ASI);
 259     bool AsiIsPartialStore(ASI);
 260     bool AsiIsFloatingLoad(ASI);
 261     bool AsiIsNoFault(ASI);
 262     bool AsiIsScratchPad(ASI);
 263     bool AsiIsCmt(ASI);
 264     bool AsiIsQueue(ASI);
 265     bool AsiIsDtlb(ASI);
 266     bool AsiIsMmu(ASI);
 267     bool AsiIsUnPriv(ASI);
 268     bool AsiIsPriv(ASI);
 269     bool AsiIsHPriv(ASI);
 270     bool AsiIsReg(ASI);
 271
 272 };
 273
 274 #endif // __ARCH_SPARC_ASI_HH__