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31 #ifndef __ARCH_SPARC_DECODER_HH__
32 #define __ARCH_SPARC_DECODER_HH__
34 #include "arch/generic/decode_cache.hh"
35 #include "arch/sparc/registers.hh"
36 #include "arch/types.hh"
37 #include "cpu/static_inst.hh"
45 // The extended machine instruction being generated
51 Decoder() : instDone(false), asi(0)
62 // Use this to give data to the predecoder. This should be used
63 // when there is control flow.
65 moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
68 // The I bit, bit 13, is used to figure out where the ASI
69 // should come from. Use that in the ExtMachInst. This is
70 // slightly redundant, but it removes the need to put a condition
71 // into all the execute functions
72 if (inst & (1 << 13)) {
73 emi |= (static_cast<ExtMachInst>(
74 asi << (sizeof(MachInst) * 8)));
76 emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
77 << (sizeof(MachInst) * 8));
95 setContext(MiscReg _asi)
100 void takeOverFrom(Decoder *old) {}
103 /// A cache of decoded instruction objects.
104 static GenericISA::BasicDecodeCache defaultCache;
107 StaticInstPtr decodeInst(ExtMachInst mach_inst);
109 /// Decode a machine instruction.
110 /// @param mach_inst The binary instruction to decode.
111 /// @retval A pointer to the corresponding StaticInst object.
113 decode(ExtMachInst mach_inst, Addr addr)
115 return defaultCache.decode(this, mach_inst, addr);
119 decode(SparcISA::PCState &nextPC)
124 return decode(emi, nextPC.instAddr());
128 } // namespace SparcISA
130 #endif // __ARCH_SPARC_DECODER_HH__