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34 #include "arch/sparc/faults.hh"
35 #include "arch/sparc/isa_traits.hh"
36 #include "arch/sparc/types.hh"
37 #include "base/bitfield.hh"
38 #include "base/trace.hh"
39 #include "config/full_system.hh"
40 #include "cpu/base.hh"
41 #include "cpu/thread_context.hh"
43 #include "arch/sparc/process.hh"
44 #include "mem/page_table.hh"
45 #include "sim/process.hh"
53 template<> SparcFaultBase::FaultVals
54 SparcFault
<PowerOnReset
>::vals
=
55 {"power_on_reset", 0x001, 0, {H
, H
, H
}};
57 template<> SparcFaultBase::FaultVals
58 SparcFault
<WatchDogReset
>::vals
=
59 {"watch_dog_reset", 0x002, 120, {H
, H
, H
}};
61 template<> SparcFaultBase::FaultVals
62 SparcFault
<ExternallyInitiatedReset
>::vals
=
63 {"externally_initiated_reset", 0x003, 110, {H
, H
, H
}};
65 template<> SparcFaultBase::FaultVals
66 SparcFault
<SoftwareInitiatedReset
>::vals
=
67 {"software_initiated_reset", 0x004, 130, {SH
, SH
, H
}};
69 template<> SparcFaultBase::FaultVals
70 SparcFault
<REDStateException
>::vals
=
71 {"RED_state_exception", 0x005, 1, {H
, H
, H
}};
73 template<> SparcFaultBase::FaultVals
74 SparcFault
<StoreError
>::vals
=
75 {"store_error", 0x007, 201, {H
, H
, H
}};
77 template<> SparcFaultBase::FaultVals
78 SparcFault
<InstructionAccessException
>::vals
=
79 {"instruction_access_exception", 0x008, 300, {H
, H
, H
}};
81 //XXX This trap is apparently dropped from ua2005
82 /*template<> SparcFaultBase::FaultVals
83 SparcFault<InstructionAccessMMUMiss>::vals =
84 {"inst_mmu", 0x009, 2, {H, H, H}};*/
86 template<> SparcFaultBase::FaultVals
87 SparcFault
<InstructionAccessError
>::vals
=
88 {"instruction_access_error", 0x00A, 400, {H
, H
, H
}};
90 template<> SparcFaultBase::FaultVals
91 SparcFault
<IllegalInstruction
>::vals
=
92 {"illegal_instruction", 0x010, 620, {H
, H
, H
}};
94 template<> SparcFaultBase::FaultVals
95 SparcFault
<PrivilegedOpcode
>::vals
=
96 {"privileged_opcode", 0x011, 700, {P
, SH
, SH
}};
98 //XXX This trap is apparently dropped from ua2005
99 /*template<> SparcFaultBase::FaultVals
100 SparcFault<UnimplementedLDD>::vals =
101 {"unimp_ldd", 0x012, 6, {H, H, H}};*/
103 //XXX This trap is apparently dropped from ua2005
104 /*template<> SparcFaultBase::FaultVals
105 SparcFault<UnimplementedSTD>::vals =
106 {"unimp_std", 0x013, 6, {H, H, H}};*/
108 template<> SparcFaultBase::FaultVals
109 SparcFault
<FpDisabled
>::vals
=
110 {"fp_disabled", 0x020, 800, {P
, P
, H
}};
112 template<> SparcFaultBase::FaultVals
113 SparcFault
<FpExceptionIEEE754
>::vals
=
114 {"fp_exception_ieee_754", 0x021, 1110, {P
, P
, H
}};
116 template<> SparcFaultBase::FaultVals
117 SparcFault
<FpExceptionOther
>::vals
=
118 {"fp_exception_other", 0x022, 1110, {P
, P
, H
}};
120 template<> SparcFaultBase::FaultVals
121 SparcFault
<TagOverflow
>::vals
=
122 {"tag_overflow", 0x023, 1400, {P
, P
, H
}};
124 template<> SparcFaultBase::FaultVals
125 SparcFault
<CleanWindow
>::vals
=
126 {"clean_window", 0x024, 1010, {P
, P
, H
}};
128 template<> SparcFaultBase::FaultVals
129 SparcFault
<DivisionByZero
>::vals
=
130 {"division_by_zero", 0x028, 1500, {P
, P
, H
}};
132 template<> SparcFaultBase::FaultVals
133 SparcFault
<InternalProcessorError
>::vals
=
134 {"internal_processor_error", 0x029, 4, {H
, H
, H
}};
136 template<> SparcFaultBase::FaultVals
137 SparcFault
<InstructionInvalidTSBEntry
>::vals
=
138 {"instruction_invalid_tsb_entry", 0x02A, 210, {H
, H
, SH
}};
140 template<> SparcFaultBase::FaultVals
141 SparcFault
<DataInvalidTSBEntry
>::vals
=
142 {"data_invalid_tsb_entry", 0x02B, 1203, {H
, H
, H
}};
144 template<> SparcFaultBase::FaultVals
145 SparcFault
<DataAccessException
>::vals
=
146 {"data_access_exception", 0x030, 1201, {H
, H
, H
}};
148 //XXX This trap is apparently dropped from ua2005
149 /*template<> SparcFaultBase::FaultVals
150 SparcFault<DataAccessMMUMiss>::vals =
151 {"data_mmu", 0x031, 12, {H, H, H}};*/
153 template<> SparcFaultBase::FaultVals
154 SparcFault
<DataAccessError
>::vals
=
155 {"data_access_error", 0x032, 1210, {H
, H
, H
}};
157 template<> SparcFaultBase::FaultVals
158 SparcFault
<DataAccessProtection
>::vals
=
159 {"data_access_protection", 0x033, 1207, {H
, H
, H
}};
161 template<> SparcFaultBase::FaultVals
162 SparcFault
<MemAddressNotAligned
>::vals
=
163 {"mem_address_not_aligned", 0x034, 1020, {H
, H
, H
}};
165 template<> SparcFaultBase::FaultVals
166 SparcFault
<LDDFMemAddressNotAligned
>::vals
=
167 {"LDDF_mem_address_not_aligned", 0x035, 1010, {H
, H
, H
}};
169 template<> SparcFaultBase::FaultVals
170 SparcFault
<STDFMemAddressNotAligned
>::vals
=
171 {"STDF_mem_address_not_aligned", 0x036, 1010, {H
, H
, H
}};
173 template<> SparcFaultBase::FaultVals
174 SparcFault
<PrivilegedAction
>::vals
=
175 {"privileged_action", 0x037, 1110, {H
, H
, SH
}};
177 template<> SparcFaultBase::FaultVals
178 SparcFault
<LDQFMemAddressNotAligned
>::vals
=
179 {"LDQF_mem_address_not_aligned", 0x038, 1010, {H
, H
, H
}};
181 template<> SparcFaultBase::FaultVals
182 SparcFault
<STQFMemAddressNotAligned
>::vals
=
183 {"STQF_mem_address_not_aligned", 0x039, 1010, {H
, H
, H
}};
185 template<> SparcFaultBase::FaultVals
186 SparcFault
<InstructionRealTranslationMiss
>::vals
=
187 {"instruction_real_translation_miss", 0x03E, 208, {H
, H
, SH
}};
189 template<> SparcFaultBase::FaultVals
190 SparcFault
<DataRealTranslationMiss
>::vals
=
191 {"data_real_translation_miss", 0x03F, 1203, {H
, H
, H
}};
193 //XXX This trap is apparently dropped from ua2005
194 /*template<> SparcFaultBase::FaultVals
195 SparcFault<AsyncDataError>::vals =
196 {"async_data", 0x040, 2, {H, H, H}};*/
198 template<> SparcFaultBase::FaultVals
199 SparcFault
<InterruptLevelN
>::vals
=
200 {"interrupt_level_n", 0x040, 0, {P
, P
, SH
}};
202 template<> SparcFaultBase::FaultVals
203 SparcFault
<HstickMatch
>::vals
=
204 {"hstick_match", 0x05E, 1601, {H
, H
, H
}};
206 template<> SparcFaultBase::FaultVals
207 SparcFault
<TrapLevelZero
>::vals
=
208 {"trap_level_zero", 0x05F, 202, {H
, H
, SH
}};
210 template<> SparcFaultBase::FaultVals
211 SparcFault
<InterruptVector
>::vals
=
212 {"interrupt_vector", 0x060, 2630, {H
, H
, H
}};
214 template<> SparcFaultBase::FaultVals
215 SparcFault
<PAWatchpoint
>::vals
=
216 {"PA_watchpoint", 0x061, 1209, {H
, H
, H
}};
218 template<> SparcFaultBase::FaultVals
219 SparcFault
<VAWatchpoint
>::vals
=
220 {"VA_watchpoint", 0x062, 1120, {P
, P
, SH
}};
222 template<> SparcFaultBase::FaultVals
223 SparcFault
<FastInstructionAccessMMUMiss
>::vals
=
224 {"fast_instruction_access_MMU_miss", 0x064, 208, {H
, H
, SH
}};
226 template<> SparcFaultBase::FaultVals
227 SparcFault
<FastDataAccessMMUMiss
>::vals
=
228 {"fast_data_access_MMU_miss", 0x068, 1203, {H
, H
, H
}};
230 template<> SparcFaultBase::FaultVals
231 SparcFault
<FastDataAccessProtection
>::vals
=
232 {"fast_data_access_protection", 0x06C, 1207, {H
, H
, H
}};
234 template<> SparcFaultBase::FaultVals
235 SparcFault
<InstructionBreakpoint
>::vals
=
236 {"instruction_break", 0x076, 610, {H
, H
, H
}};
238 template<> SparcFaultBase::FaultVals
239 SparcFault
<CpuMondo
>::vals
=
240 {"cpu_mondo", 0x07C, 1608, {P
, P
, SH
}};
242 template<> SparcFaultBase::FaultVals
243 SparcFault
<DevMondo
>::vals
=
244 {"dev_mondo", 0x07D, 1611, {P
, P
, SH
}};
246 template<> SparcFaultBase::FaultVals
247 SparcFault
<ResumableError
>::vals
=
248 {"resume_error", 0x07E, 3330, {P
, P
, SH
}};
250 template<> SparcFaultBase::FaultVals
251 SparcFault
<SpillNNormal
>::vals
=
252 {"spill_n_normal", 0x080, 900, {P
, P
, H
}};
254 template<> SparcFaultBase::FaultVals
255 SparcFault
<SpillNOther
>::vals
=
256 {"spill_n_other", 0x0A0, 900, {P
, P
, H
}};
258 template<> SparcFaultBase::FaultVals
259 SparcFault
<FillNNormal
>::vals
=
260 {"fill_n_normal", 0x0C0, 900, {P
, P
, H
}};
262 template<> SparcFaultBase::FaultVals
263 SparcFault
<FillNOther
>::vals
=
264 {"fill_n_other", 0x0E0, 900, {P
, P
, H
}};
266 template<> SparcFaultBase::FaultVals
267 SparcFault
<TrapInstruction
>::vals
=
268 {"trap_instruction", 0x100, 1602, {P
, P
, H
}};
271 * This causes the thread context to enter RED state. This causes the side
272 * effects which go with entering RED state because of a trap.
276 enterREDState(ThreadContext
*tc
)
278 //@todo Disable the mmu?
279 //@todo Disable watchpoints?
280 MiscReg HPSTATE
= tc
->readMiscRegNoEffect(MISCREG_HPSTATE
);
285 tc
->setMiscReg(MISCREG_HPSTATE
, HPSTATE
);
286 // PSTATE.priv is set to 1 here. The manual says it should be 0, but
287 // Legion sets it to 1.
288 MiscReg PSTATE
= tc
->readMiscRegNoEffect(MISCREG_PSTATE
);
290 tc
->setMiscReg(MISCREG_PSTATE
, PSTATE
);
294 * This sets everything up for a RED state trap except for actually jumping to
299 doREDFault(ThreadContext
*tc
, TrapType tt
)
301 MiscReg TL
= tc
->readMiscRegNoEffect(MISCREG_TL
);
302 MiscReg TSTATE
= tc
->readMiscRegNoEffect(MISCREG_TSTATE
);
303 MiscReg PSTATE
= tc
->readMiscRegNoEffect(MISCREG_PSTATE
);
304 MiscReg HPSTATE
= tc
->readMiscRegNoEffect(MISCREG_HPSTATE
);
305 MiscReg CCR
= tc
->readIntReg(NumIntArchRegs
+ 2);
306 MiscReg ASI
= tc
->readMiscRegNoEffect(MISCREG_ASI
);
307 MiscReg CWP
= tc
->readMiscRegNoEffect(MISCREG_CWP
);
308 MiscReg CANSAVE
= tc
->readMiscRegNoEffect(NumIntArchRegs
+ 3);
309 MiscReg GL
= tc
->readMiscRegNoEffect(MISCREG_GL
);
310 PCState pc
= tc
->pcState();
314 Addr pcMask
= bits(PSTATE
, 3) ? mask(32) : mask(64);
316 // set TSTATE.gl to gl
317 replaceBits(TSTATE
, 42, 40, GL
);
318 // set TSTATE.ccr to ccr
319 replaceBits(TSTATE
, 39, 32, CCR
);
320 // set TSTATE.asi to asi
321 replaceBits(TSTATE
, 31, 24, ASI
);
322 // set TSTATE.pstate to pstate
323 replaceBits(TSTATE
, 20, 8, PSTATE
);
324 // set TSTATE.cwp to cwp
325 replaceBits(TSTATE
, 4, 0, CWP
);
328 tc
->setMiscRegNoEffect(MISCREG_TSTATE
, TSTATE
);
331 tc
->setMiscRegNoEffect(MISCREG_TPC
, pc
.pc() & pcMask
);
333 tc
->setMiscRegNoEffect(MISCREG_TNPC
, pc
.npc() & pcMask
);
335 // set HTSTATE.hpstate to hpstate
336 tc
->setMiscRegNoEffect(MISCREG_HTSTATE
, HPSTATE
);
339 tc
->setMiscRegNoEffect(MISCREG_TT
, tt
);
342 tc
->setMiscReg(MISCREG_GL
, min
<int>(GL
+1, MaxGL
));
344 PSTATE
= mbits(PSTATE
, 2, 2); // just save the priv bit
345 PSTATE
|= (1 << 4); // set PSTATE.pef to 1
346 tc
->setMiscRegNoEffect(MISCREG_PSTATE
, PSTATE
);
348 // set HPSTATE.red to 1
350 // set HPSTATE.hpriv to 1
352 // set HPSTATE.ibe to 0
353 HPSTATE
&= ~(1 << 10);
354 // set HPSTATE.tlz to 0
355 HPSTATE
&= ~(1 << 0);
356 tc
->setMiscRegNoEffect(MISCREG_HPSTATE
, HPSTATE
);
358 bool changedCWP
= true;
361 else if (0x80 <= tt
&& tt
<= 0xbf)
362 CWP
+= (CANSAVE
+ 2);
363 else if (0xc0 <= tt
&& tt
<= 0xff)
369 CWP
= (CWP
+ NWindows
) % NWindows
;
370 tc
->setMiscReg(MISCREG_CWP
, CWP
);
375 * This sets everything up for a normal trap except for actually jumping to
380 doNormalFault(ThreadContext
*tc
, TrapType tt
, bool gotoHpriv
)
382 MiscReg TL
= tc
->readMiscRegNoEffect(MISCREG_TL
);
383 MiscReg TSTATE
= tc
->readMiscRegNoEffect(MISCREG_TSTATE
);
384 MiscReg PSTATE
= tc
->readMiscRegNoEffect(MISCREG_PSTATE
);
385 MiscReg HPSTATE
= tc
->readMiscRegNoEffect(MISCREG_HPSTATE
);
386 MiscReg CCR
= tc
->readIntReg(NumIntArchRegs
+ 2);
387 MiscReg ASI
= tc
->readMiscRegNoEffect(MISCREG_ASI
);
388 MiscReg CWP
= tc
->readMiscRegNoEffect(MISCREG_CWP
);
389 MiscReg CANSAVE
= tc
->readIntReg(NumIntArchRegs
+ 3);
390 MiscReg GL
= tc
->readMiscRegNoEffect(MISCREG_GL
);
391 PCState pc
= tc
->pcState();
393 // Increment the trap level
395 tc
->setMiscRegNoEffect(MISCREG_TL
, TL
);
397 Addr pcMask
= bits(PSTATE
, 3) ? mask(32) : mask(64);
401 // set TSTATE.gl to gl
402 replaceBits(TSTATE
, 42, 40, GL
);
403 // set TSTATE.ccr to ccr
404 replaceBits(TSTATE
, 39, 32, CCR
);
405 // set TSTATE.asi to asi
406 replaceBits(TSTATE
, 31, 24, ASI
);
407 // set TSTATE.pstate to pstate
408 replaceBits(TSTATE
, 20, 8, PSTATE
);
409 // set TSTATE.cwp to cwp
410 replaceBits(TSTATE
, 4, 0, CWP
);
413 tc
->setMiscRegNoEffect(MISCREG_TSTATE
, TSTATE
);
416 tc
->setMiscRegNoEffect(MISCREG_TPC
, pc
.pc() & pcMask
);
418 tc
->setMiscRegNoEffect(MISCREG_TNPC
, pc
.npc() & pcMask
);
420 // set HTSTATE.hpstate to hpstate
421 tc
->setMiscRegNoEffect(MISCREG_HTSTATE
, HPSTATE
);
424 tc
->setMiscRegNoEffect(MISCREG_TT
, tt
);
426 // Update the global register level
428 tc
->setMiscReg(MISCREG_GL
, min
<int>(GL
+ 1, MaxPGL
));
430 tc
->setMiscReg(MISCREG_GL
, min
<int>(GL
+ 1, MaxGL
));
432 // PSTATE.mm is unchanged
433 PSTATE
|= (1 << 4); // PSTATE.pef = whether or not an fpu is present
434 PSTATE
&= ~(1 << 3); // PSTATE.am = 0
435 PSTATE
&= ~(1 << 1); // PSTATE.ie = 0
436 // PSTATE.tle is unchanged
440 PSTATE
&= ~(1 << 9); // PSTATE.cle = 0
441 // The manual says PSTATE.priv should be 0, but Legion leaves it alone
442 HPSTATE
&= ~(1 << 5); // HPSTATE.red = 0
443 HPSTATE
|= (1 << 2); // HPSTATE.hpriv = 1
444 HPSTATE
&= ~(1 << 10); // HPSTATE.ibe = 0
445 // HPSTATE.tlz is unchanged
446 tc
->setMiscRegNoEffect(MISCREG_HPSTATE
, HPSTATE
);
447 } else { // we are going to priv
448 PSTATE
|= (1 << 2); // PSTATE.priv = 1
449 replaceBits(PSTATE
, 9, 9, PSTATE
>> 8); // PSTATE.cle = PSTATE.tle
451 tc
->setMiscRegNoEffect(MISCREG_PSTATE
, PSTATE
);
454 bool changedCWP
= true;
457 else if (0x80 <= tt
&& tt
<= 0xbf)
458 CWP
+= (CANSAVE
+ 2);
459 else if (0xc0 <= tt
&& tt
<= 0xff)
465 CWP
= (CWP
+ NWindows
) % NWindows
;
466 tc
->setMiscReg(MISCREG_CWP
, CWP
);
471 getREDVector(MiscReg TT
, Addr
&PC
, Addr
&NPC
)
473 //XXX The following constant might belong in a header file.
474 const Addr RSTVAddr
= 0xFFF0000000ULL
;
475 PC
= RSTVAddr
| ((TT
<< 5) & 0xFF);
476 NPC
= PC
+ sizeof(MachInst
);
480 getHyperVector(ThreadContext
* tc
, Addr
&PC
, Addr
&NPC
, MiscReg TT
)
482 Addr HTBA
= tc
->readMiscRegNoEffect(MISCREG_HTBA
);
483 PC
= (HTBA
& ~mask(14)) | ((TT
<< 5) & mask(14));
484 NPC
= PC
+ sizeof(MachInst
);
488 getPrivVector(ThreadContext
*tc
, Addr
&PC
, Addr
&NPC
, MiscReg TT
, MiscReg TL
)
490 Addr TBA
= tc
->readMiscRegNoEffect(MISCREG_TBA
);
491 PC
= (TBA
& ~mask(15)) |
492 (TL
> 1 ? (1 << 14) : 0) |
493 ((TT
<< 5) & mask(14));
494 NPC
= PC
+ sizeof(MachInst
);
500 SparcFaultBase::invoke(ThreadContext
* tc
, StaticInstPtr inst
)
502 FaultBase::invoke(tc
);
505 // We can refer to this to see what the trap level -was-, but something
506 // in the middle could change it in the regfile out from under us.
507 MiscReg tl
= tc
->readMiscRegNoEffect(MISCREG_TL
);
508 MiscReg tt
= tc
->readMiscRegNoEffect(MISCREG_TT
);
509 MiscReg pstate
= tc
->readMiscRegNoEffect(MISCREG_PSTATE
);
510 MiscReg hpstate
= tc
->readMiscRegNoEffect(MISCREG_HPSTATE
);
514 PrivilegeLevel current
;
515 if (hpstate
& HPSTATE::hpriv
)
516 current
= Hyperprivileged
;
517 else if (pstate
& PSTATE::priv
)
518 current
= Privileged
;
522 PrivilegeLevel level
= getNextLevel(current
);
524 if ((hpstate
& HPSTATE::red
) || (tl
== MaxTL
- 1)) {
525 getREDVector(5, PC
, NPC
);
527 // This changes the hpstate and pstate, so we need to make sure we
528 // save the old version on the trap stack in doREDFault.
530 } else if (tl
== MaxTL
) {
531 panic("Should go to error state here.. crap\n");
532 // Do error_state somehow?
533 // Probably inject a WDR fault using the interrupt mechanism.
534 // What should the PC and NPC be set to?
535 } else if (tl
> MaxPTL
&& level
== Privileged
) {
536 // guest_watchdog fault
537 doNormalFault(tc
, trapType(), true);
538 getHyperVector(tc
, PC
, NPC
, 2);
539 } else if (level
== Hyperprivileged
||
540 (level
== Privileged
&& trapType() >= 384)) {
541 doNormalFault(tc
, trapType(), true);
542 getHyperVector(tc
, PC
, NPC
, trapType());
544 doNormalFault(tc
, trapType(), false);
545 getPrivVector(tc
, PC
, NPC
, trapType(), tl
+ 1);
551 pc
.nnpc(NPC
+ sizeof(MachInst
));
558 PowerOnReset::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
560 // For SPARC, when a system is first started, there is a power
561 // on reset Trap which sets the processor into the following state.
562 // Bits that aren't set aren't defined on startup.
564 tc
->setMiscRegNoEffect(MISCREG_TL
, MaxTL
);
565 tc
->setMiscRegNoEffect(MISCREG_TT
, trapType());
566 tc
->setMiscReg(MISCREG_GL
, MaxGL
);
568 // Turn on pef and priv, set everything else to 0
569 tc
->setMiscRegNoEffect(MISCREG_PSTATE
, (1 << 4) | (1 << 2));
571 // Turn on red and hpriv, set everything else to 0
572 MiscReg HPSTATE
= tc
->readMiscRegNoEffect(MISCREG_HPSTATE
);
578 HPSTATE
&= ~(1 << 10);
580 HPSTATE
&= ~(1 << 0);
581 tc
->setMiscRegNoEffect(MISCREG_HPSTATE
, HPSTATE
);
583 // The tick register is unreadable by nonprivileged software
584 tc
->setMiscRegNoEffect(MISCREG_TICK
, 1ULL << 63);
586 // Enter RED state. We do this last so that the actual state preserved in
587 // the trap stack is the state from before this fault.
591 getREDVector(trapType(), PC
, NPC
);
596 pc
.nnpc(NPC
+ sizeof(MachInst
));
601 // These registers are specified as "undefined" after a POR, and they
602 // should have reasonable values after the miscregfile is reset
604 // Clear all the soft interrupt bits
606 // disable timer compare interrupts, reset tick_cmpr
607 tc->setMiscRegNoEffect(MISCREG_
608 tick_cmprFields.int_dis = 1;
609 tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
610 stickFields.npt = 1; // The TICK register is unreadable by by !priv
611 stick_cmprFields.int_dis = 1; // disable timer compare interrupts
612 stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
616 hintp = 0; // no interrupts pending
617 hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
618 hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
622 #else // !FULL_SYSTEM
625 FastInstructionAccessMMUMiss::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
627 Process
*p
= tc
->getProcessPtr();
629 bool success
= p
->pTable
->lookup(vaddr
, entry
);
631 panic("Tried to execute unmapped address %#x.\n", vaddr
);
633 Addr alignedVaddr
= p
->pTable
->pageAlign(vaddr
);
634 tc
->getITBPtr()->insert(alignedVaddr
, 0 /*partition id*/,
635 p
->M5_pid
/*context id*/, false, entry
.pte
);
640 FastDataAccessMMUMiss::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
642 Process
*p
= tc
->getProcessPtr();
644 bool success
= p
->pTable
->lookup(vaddr
, entry
);
646 if (p
->fixupStackFault(vaddr
))
647 success
= p
->pTable
->lookup(vaddr
, entry
);
650 panic("Tried to access unmapped address %#x.\n", vaddr
);
652 Addr alignedVaddr
= p
->pTable
->pageAlign(vaddr
);
653 tc
->getDTBPtr()->insert(alignedVaddr
, 0 /*partition id*/,
654 p
->M5_pid
/*context id*/, false, entry
.pte
);
659 SpillNNormal::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
661 doNormalFault(tc
, trapType(), false);
663 Process
*p
= tc
->getProcessPtr();
665 //XXX This will only work in faults from a SparcLiveProcess
666 SparcLiveProcess
*lp
= dynamic_cast<SparcLiveProcess
*>(p
);
669 // Then adjust the PC and NPC
670 tc
->pcState(lp
->readSpillStart());
674 FillNNormal::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
676 doNormalFault(tc
, trapType(), false);
678 Process
*p
= tc
->getProcessPtr();
680 //XXX This will only work in faults from a SparcLiveProcess
681 SparcLiveProcess
*lp
= dynamic_cast<SparcLiveProcess
*>(p
);
684 // Then adjust the PC and NPC
685 tc
->pcState(lp
->readFillStart());
689 TrapInstruction::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
691 // In SE, this mechanism is how the process requests a service from the
692 // operating system. We'll get the process object from the thread context
693 // and let it service the request.
695 Process
*p
= tc
->getProcessPtr();
697 SparcLiveProcess
*lp
= dynamic_cast<SparcLiveProcess
*>(p
);
700 lp
->handleTrap(_n
, tc
);
702 // We need to explicitly advance the pc, since that's not done for us
703 // on a faulting instruction
704 PCState pc
= tc
->pcState();
711 } // namespace SparcISA