src/arch/sparc/faults.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Kevin Lim
  30  */
  31
  32 #include <algorithm>
  33
  34 #include "arch/sparc/faults.hh"
  35 #include "arch/sparc/isa_traits.hh"
  36 #include "arch/sparc/types.hh"
  37 #include "base/bitfield.hh"
  38 #include "base/trace.hh"
  39 #include "config/full_system.hh"
  40 #include "cpu/base.hh"
  41 #include "cpu/thread_context.hh"
  42 #if !FULL_SYSTEM
  43 #include "arch/sparc/process.hh"
  44 #include "mem/page_table.hh"
  45 #include "sim/process.hh"
  46 #endif
  47
  48 using namespace std;
  49
  50 namespace SparcISA
  51 {
  52
  53 template<> SparcFaultBase::FaultVals
  54     SparcFault<PowerOnReset>::vals =
  55     {"power_on_reset", 0x001, 0, {H, H, H}};
  56
  57 template<> SparcFaultBase::FaultVals
  58     SparcFault<WatchDogReset>::vals =
  59     {"watch_dog_reset", 0x002, 120, {H, H, H}};
  60
  61 template<> SparcFaultBase::FaultVals
  62     SparcFault<ExternallyInitiatedReset>::vals =
  63     {"externally_initiated_reset", 0x003, 110, {H, H, H}};
  64
  65 template<> SparcFaultBase::FaultVals
  66     SparcFault<SoftwareInitiatedReset>::vals =
  67     {"software_initiated_reset", 0x004, 130, {SH, SH, H}};
  68
  69 template<> SparcFaultBase::FaultVals
  70     SparcFault<REDStateException>::vals =
  71     {"RED_state_exception", 0x005, 1, {H, H, H}};
  72
  73 template<> SparcFaultBase::FaultVals
  74     SparcFault<StoreError>::vals =
  75     {"store_error", 0x007, 201, {H, H, H}};
  76
  77 template<> SparcFaultBase::FaultVals
  78     SparcFault<InstructionAccessException>::vals =
  79     {"instruction_access_exception", 0x008, 300, {H, H, H}};
  80
  81 //XXX This trap is apparently dropped from ua2005
  82 /*template<> SparcFaultBase::FaultVals
  83     SparcFault<InstructionAccessMMUMiss>::vals =
  84     {"inst_mmu", 0x009, 2, {H, H, H}};*/
  85
  86 template<> SparcFaultBase::FaultVals
  87     SparcFault<InstructionAccessError>::vals =
  88     {"instruction_access_error", 0x00A, 400, {H, H, H}};
  89
  90 template<> SparcFaultBase::FaultVals
  91     SparcFault<IllegalInstruction>::vals =
  92     {"illegal_instruction", 0x010, 620, {H, H, H}};
  93
  94 template<> SparcFaultBase::FaultVals
  95     SparcFault<PrivilegedOpcode>::vals =
  96     {"privileged_opcode", 0x011, 700, {P, SH, SH}};
  97
  98 //XXX This trap is apparently dropped from ua2005
  99 /*template<> SparcFaultBase::FaultVals
 100     SparcFault<UnimplementedLDD>::vals =
 101     {"unimp_ldd", 0x012, 6, {H, H, H}};*/
 102
 103 //XXX This trap is apparently dropped from ua2005
 104 /*template<> SparcFaultBase::FaultVals
 105     SparcFault<UnimplementedSTD>::vals =
 106     {"unimp_std", 0x013, 6, {H, H, H}};*/
 107
 108 template<> SparcFaultBase::FaultVals
 109     SparcFault<FpDisabled>::vals =
 110     {"fp_disabled", 0x020, 800, {P, P, H}};
 111
 112 template<> SparcFaultBase::FaultVals
 113     SparcFault<FpExceptionIEEE754>::vals =
 114     {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}};
 115
 116 template<> SparcFaultBase::FaultVals
 117     SparcFault<FpExceptionOther>::vals =
 118     {"fp_exception_other", 0x022, 1110, {P, P, H}};
 119
 120 template<> SparcFaultBase::FaultVals
 121     SparcFault<TagOverflow>::vals =
 122     {"tag_overflow", 0x023, 1400, {P, P, H}};
 123
 124 template<> SparcFaultBase::FaultVals
 125     SparcFault<CleanWindow>::vals =
 126     {"clean_window", 0x024, 1010, {P, P, H}};
 127
 128 template<> SparcFaultBase::FaultVals
 129     SparcFault<DivisionByZero>::vals =
 130     {"division_by_zero", 0x028, 1500, {P, P, H}};
 131
 132 template<> SparcFaultBase::FaultVals
 133     SparcFault<InternalProcessorError>::vals =
 134     {"internal_processor_error", 0x029, 4, {H, H, H}};
 135
 136 template<> SparcFaultBase::FaultVals
 137     SparcFault<InstructionInvalidTSBEntry>::vals =
 138     {"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}};
 139
 140 template<> SparcFaultBase::FaultVals
 141     SparcFault<DataInvalidTSBEntry>::vals =
 142     {"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}};
 143
 144 template<> SparcFaultBase::FaultVals
 145     SparcFault<DataAccessException>::vals =
 146     {"data_access_exception", 0x030, 1201, {H, H, H}};
 147
 148 //XXX This trap is apparently dropped from ua2005
 149 /*template<> SparcFaultBase::FaultVals
 150     SparcFault<DataAccessMMUMiss>::vals =
 151     {"data_mmu", 0x031, 12, {H, H, H}};*/
 152
 153 template<> SparcFaultBase::FaultVals
 154     SparcFault<DataAccessError>::vals =
 155     {"data_access_error", 0x032, 1210, {H, H, H}};
 156
 157 template<> SparcFaultBase::FaultVals
 158     SparcFault<DataAccessProtection>::vals =
 159     {"data_access_protection", 0x033, 1207, {H, H, H}};
 160
 161 template<> SparcFaultBase::FaultVals
 162     SparcFault<MemAddressNotAligned>::vals =
 163     {"mem_address_not_aligned", 0x034, 1020, {H, H, H}};
 164
 165 template<> SparcFaultBase::FaultVals
 166     SparcFault<LDDFMemAddressNotAligned>::vals =
 167     {"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}};
 168
 169 template<> SparcFaultBase::FaultVals
 170     SparcFault<STDFMemAddressNotAligned>::vals =
 171     {"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}};
 172
 173 template<> SparcFaultBase::FaultVals
 174     SparcFault<PrivilegedAction>::vals =
 175     {"privileged_action", 0x037, 1110, {H, H, SH}};
 176
 177 template<> SparcFaultBase::FaultVals
 178     SparcFault<LDQFMemAddressNotAligned>::vals =
 179     {"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}};
 180
 181 template<> SparcFaultBase::FaultVals
 182     SparcFault<STQFMemAddressNotAligned>::vals =
 183     {"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}};
 184
 185 template<> SparcFaultBase::FaultVals
 186     SparcFault<InstructionRealTranslationMiss>::vals =
 187     {"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}};
 188
 189 template<> SparcFaultBase::FaultVals
 190     SparcFault<DataRealTranslationMiss>::vals =
 191     {"data_real_translation_miss", 0x03F, 1203, {H, H, H}};
 192
 193 //XXX This trap is apparently dropped from ua2005
 194 /*template<> SparcFaultBase::FaultVals
 195     SparcFault<AsyncDataError>::vals =
 196     {"async_data", 0x040, 2, {H, H, H}};*/
 197
 198 template<> SparcFaultBase::FaultVals
 199     SparcFault<InterruptLevelN>::vals =
 200     {"interrupt_level_n", 0x040, 0, {P, P, SH}};
 201
 202 template<> SparcFaultBase::FaultVals
 203     SparcFault<HstickMatch>::vals =
 204     {"hstick_match", 0x05E, 1601, {H, H, H}};
 205
 206 template<> SparcFaultBase::FaultVals
 207     SparcFault<TrapLevelZero>::vals =
 208     {"trap_level_zero", 0x05F, 202, {H, H, SH}};
 209
 210 template<> SparcFaultBase::FaultVals
 211     SparcFault<PAWatchpoint>::vals =
 212     {"PA_watchpoint", 0x061, 1209, {H, H, H}};
 213
 214 template<> SparcFaultBase::FaultVals
 215     SparcFault<VAWatchpoint>::vals =
 216     {"VA_watchpoint", 0x062, 1120, {P, P, SH}};
 217
 218 template<> SparcFaultBase::FaultVals
 219     SparcFault<FastInstructionAccessMMUMiss>::vals =
 220     {"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}};
 221
 222 template<> SparcFaultBase::FaultVals
 223     SparcFault<FastDataAccessMMUMiss>::vals =
 224     {"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}};
 225
 226 template<> SparcFaultBase::FaultVals
 227     SparcFault<FastDataAccessProtection>::vals =
 228     {"fast_data_access_protection", 0x06C, 1207, {H, H, H}};
 229
 230 template<> SparcFaultBase::FaultVals
 231     SparcFault<InstructionBreakpoint>::vals =
 232     {"instruction_break", 0x076, 610, {H, H, H}};
 233
 234 template<> SparcFaultBase::FaultVals
 235     SparcFault<CpuMondo>::vals =
 236     {"cpu_mondo", 0x07C, 1608, {P, P, SH}};
 237
 238 template<> SparcFaultBase::FaultVals
 239     SparcFault<DevMondo>::vals =
 240     {"dev_mondo", 0x07D, 1611, {P, P, SH}};
 241
 242 template<> SparcFaultBase::FaultVals
 243     SparcFault<ResumableError>::vals =
 244     {"resume_error", 0x07E, 3330, {P, P, SH}};
 245
 246 template<> SparcFaultBase::FaultVals
 247     SparcFault<SpillNNormal>::vals =
 248     {"spill_n_normal", 0x080, 900, {P, P, H}};
 249
 250 template<> SparcFaultBase::FaultVals
 251     SparcFault<SpillNOther>::vals =
 252     {"spill_n_other", 0x0A0, 900, {P, P, H}};
 253
 254 template<> SparcFaultBase::FaultVals
 255     SparcFault<FillNNormal>::vals =
 256     {"fill_n_normal", 0x0C0, 900, {P, P, H}};
 257
 258 template<> SparcFaultBase::FaultVals
 259     SparcFault<FillNOther>::vals =
 260     {"fill_n_other", 0x0E0, 900, {P, P, H}};
 261
 262 template<> SparcFaultBase::FaultVals
 263     SparcFault<TrapInstruction>::vals =
 264     {"trap_instruction", 0x100, 1602, {P, P, H}};
 265
 266 #if !FULL_SYSTEM
 267 template<> SparcFaultBase::FaultVals
 268     SparcFault<PageTableFault>::vals =
 269     {"page_table_fault", 0x0000, 0, {SH, SH, SH}};
 270 #endif
 271
 272 /**
 273  * This causes the thread context to enter RED state. This causes the side
 274  * effects which go with entering RED state because of a trap.
 275  */
 276
 277 void enterREDState(ThreadContext *tc)
 278 {
 279     //@todo Disable the mmu?
 280     //@todo Disable watchpoints?
 281     MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
 282     //HPSTATE.red = 1
 283     HPSTATE |= (1 << 5);
 284     //HPSTATE.hpriv = 1
 285     HPSTATE |= (1 << 2);
 286     tc->setMiscRegWithEffect(MISCREG_HPSTATE, HPSTATE);
 287     //PSTATE.priv is set to 1 here. The manual says it should be 0, but
 288     //Legion sets it to 1.
 289     MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
 290     PSTATE |= (1 << 2);
 291     tc->setMiscRegWithEffect(MISCREG_PSTATE, PSTATE);
 292 }
 293
 294 /**
 295  * This sets everything up for a RED state trap except for actually jumping to
 296  * the handler.
 297  */
 298
 299 void doREDFault(ThreadContext *tc, TrapType tt)
 300 {
 301     MiscReg TL = tc->readMiscReg(MISCREG_TL);
 302     MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
 303     MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
 304     MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
 305     //MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
 306     MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
 307     MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
 308     MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
 309     //MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
 310     MiscReg CANSAVE = tc->readMiscReg(NumIntArchRegs + 3);
 311     MiscReg GL = tc->readMiscReg(MISCREG_GL);
 312     MiscReg PC = tc->readPC();
 313     MiscReg NPC = tc->readNextPC();
 314
 315     TL++;
 316
 317     if (bits(PSTATE, 3,3)) {
 318         PC &= mask(32);
 319         NPC &= mask(32);
 320     }
 321
 322     //set TSTATE.gl to gl
 323     replaceBits(TSTATE, 42, 40, GL);
 324     //set TSTATE.ccr to ccr
 325     replaceBits(TSTATE, 39, 32, CCR);
 326     //set TSTATE.asi to asi
 327     replaceBits(TSTATE, 31, 24, ASI);
 328     //set TSTATE.pstate to pstate
 329     replaceBits(TSTATE, 20, 8, PSTATE);
 330     //set TSTATE.cwp to cwp
 331     replaceBits(TSTATE, 4, 0, CWP);
 332
 333     //Write back TSTATE
 334     tc->setMiscReg(MISCREG_TSTATE, TSTATE);
 335
 336     //set TPC to PC
 337     tc->setMiscReg(MISCREG_TPC, PC);
 338     //set TNPC to NPC
 339     tc->setMiscReg(MISCREG_TNPC, NPC);
 340
 341     //set HTSTATE.hpstate to hpstate
 342     tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
 343
 344     //TT = trap type;
 345     tc->setMiscReg(MISCREG_TT, tt);
 346
 347     //Update GL
 348     tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
 349
 350     PSTATE = mbits(PSTATE, 2, 2); // just save the priv bit
 351     PSTATE |= (1 << 4); //set PSTATE.pef to 1
 352     tc->setMiscReg(MISCREG_PSTATE, PSTATE);
 353
 354     //set HPSTATE.red to 1
 355     HPSTATE |= (1 << 5);
 356     //set HPSTATE.hpriv to 1
 357     HPSTATE |= (1 << 2);
 358     //set HPSTATE.ibe to 0
 359     HPSTATE &= ~(1 << 10);
 360     //set HPSTATE.tlz to 0
 361     HPSTATE &= ~(1 << 0);
 362     tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
 363
 364     bool changedCWP = true;
 365     if(tt == 0x24)
 366         CWP++;
 367     else if(0x80 <= tt && tt <= 0xbf)
 368         CWP += (CANSAVE + 2);
 369     else if(0xc0 <= tt && tt <= 0xff)
 370         CWP--;
 371     else
 372         changedCWP = false;
 373
 374     if(changedCWP)
 375     {
 376         CWP = (CWP + NWindows) % NWindows;
 377         tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
 378     }
 379 }
 380
 381 /**
 382  * This sets everything up for a normal trap except for actually jumping to
 383  * the handler.
 384  */
 385
 386 void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
 387 {
 388     MiscReg TL = tc->readMiscReg(MISCREG_TL);
 389     MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
 390     MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
 391     MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
 392     //MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
 393     MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
 394     MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
 395     MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
 396     //MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
 397     MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
 398     MiscReg GL = tc->readMiscReg(MISCREG_GL);
 399     MiscReg PC = tc->readPC();
 400     MiscReg NPC = tc->readNextPC();
 401
 402     if (bits(PSTATE, 3,3)) {
 403         PC &= mask(32);
 404         NPC &= mask(32);
 405     }
 406
 407     //Increment the trap level
 408     TL++;
 409     tc->setMiscReg(MISCREG_TL, TL);
 410
 411     //Save off state
 412
 413     //set TSTATE.gl to gl
 414     replaceBits(TSTATE, 42, 40, GL);
 415     //set TSTATE.ccr to ccr
 416     replaceBits(TSTATE, 39, 32, CCR);
 417     //set TSTATE.asi to asi
 418     replaceBits(TSTATE, 31, 24, ASI);
 419     //set TSTATE.pstate to pstate
 420     replaceBits(TSTATE, 20, 8, PSTATE);
 421     //set TSTATE.cwp to cwp
 422     replaceBits(TSTATE, 4, 0, CWP);
 423
 424     //Write back TSTATE
 425     tc->setMiscReg(MISCREG_TSTATE, TSTATE);
 426
 427     //set TPC to PC
 428     tc->setMiscReg(MISCREG_TPC, PC);
 429     //set TNPC to NPC
 430     tc->setMiscReg(MISCREG_TNPC, NPC);
 431
 432     //set HTSTATE.hpstate to hpstate
 433     tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
 434
 435     //TT = trap type;
 436     tc->setMiscReg(MISCREG_TT, tt);
 437
 438     //Update the global register level
 439     if (!gotoHpriv)
 440         tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxPGL));
 441     else
 442         tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
 443
 444     //PSTATE.mm is unchanged
 445     PSTATE |= (1 << 4); //PSTATE.pef = whether or not an fpu is present
 446     PSTATE &= ~(1 << 3); //PSTATE.am = 0
 447     PSTATE &= ~(1 << 1); //PSTATE.ie = 0
 448     //PSTATE.tle is unchanged
 449     //PSTATE.tct = 0
 450
 451     if (gotoHpriv)
 452     {
 453         PSTATE &= ~(1 << 9); // PSTATE.cle = 0
 454         //The manual says PSTATE.priv should be 0, but Legion leaves it alone
 455         HPSTATE &= ~(1 << 5); //HPSTATE.red = 0
 456         HPSTATE |= (1 << 2); //HPSTATE.hpriv = 1
 457         HPSTATE &= ~(1 << 10); //HPSTATE.ibe = 0
 458         //HPSTATE.tlz is unchanged
 459         tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
 460     } else { // we are going to priv
 461         PSTATE |= (1 << 2); //PSTATE.priv = 1
 462         replaceBits(PSTATE, 9, 9, PSTATE >> 8); //PSTATE.cle = PSTATE.tle
 463     }
 464     tc->setMiscReg(MISCREG_PSTATE, PSTATE);
 465
 466
 467     bool changedCWP = true;
 468     if (tt == 0x24)
 469         CWP++;
 470     else if (0x80 <= tt && tt <= 0xbf)
 471         CWP += (CANSAVE + 2);
 472     else if (0xc0 <= tt && tt <= 0xff)
 473         CWP--;
 474     else
 475         changedCWP = false;
 476
 477     if (changedCWP)
 478     {
 479         CWP = (CWP + NWindows) % NWindows;
 480         tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
 481     }
 482 }
 483
 484 void getREDVector(MiscReg TT, Addr & PC, Addr & NPC)
 485 {
 486     //XXX The following constant might belong in a header file.
 487     const Addr RSTVAddr = 0xFFF0000000ULL;
 488     PC = RSTVAddr | ((TT << 5) & 0xFF);
 489     NPC = PC + sizeof(MachInst);
 490 }
 491
 492 void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT)
 493 {
 494     Addr HTBA = tc->readMiscReg(MISCREG_HTBA);
 495     PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
 496     NPC = PC + sizeof(MachInst);
 497 }
 498
 499 void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL)
 500 {
 501     Addr TBA = tc->readMiscReg(MISCREG_TBA);
 502     PC = (TBA & ~mask(15)) |
 503         (TL > 1 ? (1 << 14) : 0) |
 504         ((TT << 5) & mask(14));
 505     NPC = PC + sizeof(MachInst);
 506 }
 507
 508 #if FULL_SYSTEM
 509
 510 void SparcFaultBase::invoke(ThreadContext * tc)
 511 {
 512     //panic("Invoking a second fault!\n");
 513     FaultBase::invoke(tc);
 514     countStat()++;
 515
 516     //We can refer to this to see what the trap level -was-, but something
 517     //in the middle could change it in the regfile out from under us.
 518     MiscReg tl = tc->readMiscReg(MISCREG_TL);
 519     MiscReg tt = tc->readMiscReg(MISCREG_TT);
 520     MiscReg pstate = tc->readMiscReg(MISCREG_PSTATE);
 521     MiscReg hpstate = tc->readMiscReg(MISCREG_HPSTATE);
 522
 523     Addr PC, NPC;
 524
 525     PrivilegeLevel current;
 526     if (hpstate & HPSTATE::hpriv)
 527         current = Hyperprivileged;
 528     else if (pstate & PSTATE::priv)
 529         current = Privileged;
 530     else
 531         current = User;
 532
 533     PrivilegeLevel level = getNextLevel(current);
 534
 535     if ((hpstate & HPSTATE::red) || (tl == MaxTL - 1)) {
 536         getREDVector(5, PC, NPC);
 537         doREDFault(tc, tt);
 538         //This changes the hpstate and pstate, so we need to make sure we
 539         //save the old version on the trap stack in doREDFault.
 540         enterREDState(tc);
 541     } else if (tl == MaxTL) {
 542         panic("Should go to error state here.. crap\n");
 543         //Do error_state somehow?
 544         //Probably inject a WDR fault using the interrupt mechanism.
 545         //What should the PC and NPC be set to?
 546     } else if (tl > MaxPTL && level == Privileged) {
 547         //guest_watchdog fault
 548         doNormalFault(tc, trapType(), true);
 549         getHyperVector(tc, PC, NPC, 2);
 550     } else if (level == Hyperprivileged ||
 551             level == Privileged && trapType() >= 384) {
 552         doNormalFault(tc, trapType(), true);
 553         getHyperVector(tc, PC, NPC, trapType());
 554     } else {
 555         doNormalFault(tc, trapType(), false);
 556         getPrivVector(tc, PC, NPC, trapType(), tl+1);
 557     }
 558
 559     tc->setPC(PC);
 560     tc->setNextPC(NPC);
 561     tc->setNextNPC(NPC + sizeof(MachInst));
 562 }
 563
 564 void PowerOnReset::invoke(ThreadContext * tc)
 565 {
 566     //For SPARC, when a system is first started, there is a power
 567     //on reset Trap which sets the processor into the following state.
 568     //Bits that aren't set aren't defined on startup.
 569
 570     tc->setMiscReg(MISCREG_TL, MaxTL);
 571     tc->setMiscReg(MISCREG_TT, trapType());
 572     tc->setMiscRegWithEffect(MISCREG_GL, MaxGL);
 573
 574     //Turn on pef and priv, set everything else to 0
 575     tc->setMiscReg(MISCREG_PSTATE, (1 << 4) | (1 << 2));
 576
 577     //Turn on red and hpriv, set everything else to 0
 578     MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
 579     //HPSTATE.red = 1
 580     HPSTATE |= (1 << 5);
 581     //HPSTATE.hpriv = 1
 582     HPSTATE |= (1 << 2);
 583     //HPSTATE.ibe = 0
 584     HPSTATE &= ~(1 << 10);
 585     //HPSTATE.tlz = 0
 586     HPSTATE &= ~(1 << 0);
 587     tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
 588
 589     //The tick register is unreadable by nonprivileged software
 590     tc->setMiscReg(MISCREG_TICK, 1ULL << 63);
 591
 592     //Enter RED state. We do this last so that the actual state preserved in
 593     //the trap stack is the state from before this fault.
 594     enterREDState(tc);
 595
 596     Addr PC, NPC;
 597     getREDVector(trapType(), PC, NPC);
 598     tc->setPC(PC);
 599     tc->setNextPC(NPC);
 600     tc->setNextNPC(NPC + sizeof(MachInst));
 601
 602     //These registers are specified as "undefined" after a POR, and they
 603     //should have reasonable values after the miscregfile is reset
 604     /*
 605     // Clear all the soft interrupt bits
 606     softint = 0;
 607     // disable timer compare interrupts, reset tick_cmpr
 608     tc->setMiscReg(MISCREG_
 609     tick_cmprFields.int_dis = 1;
 610     tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
 611     stickFields.npt = 1; //The TICK register is unreadable by by !priv
 612     stick_cmprFields.int_dis = 1; // disable timer compare interrupts
 613     stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
 614
 615     tt[tl] = _trapType;
 616
 617     hintp = 0; // no interrupts pending
 618     hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
 619     hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
 620     */
 621 }
 622
 623 #else // !FULL_SYSTEM
 624
 625 void SpillNNormal::invoke(ThreadContext *tc)
 626 {
 627     doNormalFault(tc, trapType(), false);
 628
 629     Process *p = tc->getProcessPtr();
 630
 631     //XXX This will only work in faults from a SparcLiveProcess
 632     SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
 633     assert(lp);
 634
 635     //Then adjust the PC and NPC
 636     Addr spillStart = lp->readSpillStart();
 637     tc->setPC(spillStart);
 638     tc->setNextPC(spillStart + sizeof(MachInst));
 639     tc->setNextNPC(spillStart + 2*sizeof(MachInst));
 640 }
 641
 642 void FillNNormal::invoke(ThreadContext *tc)
 643 {
 644     doNormalFault(tc, trapType(), false);
 645
 646     Process * p = tc->getProcessPtr();
 647
 648     //XXX This will only work in faults from a SparcLiveProcess
 649     SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
 650     assert(lp);
 651
 652     //Then adjust the PC and NPC
 653     Addr fillStart = lp->readFillStart();
 654     tc->setPC(fillStart);
 655     tc->setNextPC(fillStart + sizeof(MachInst));
 656     tc->setNextNPC(fillStart + 2*sizeof(MachInst));
 657 }
 658
 659 void PageTableFault::invoke(ThreadContext *tc)
 660 {
 661     Process *p = tc->getProcessPtr();
 662
 663     // We've accessed the next page of the stack, so extend the stack
 664     // to cover it.
 665     if(vaddr < p->stack_min && vaddr >= p->stack_min - PageBytes)
 666     {
 667         p->stack_min -= PageBytes;
 668         if(p->stack_base - p->stack_min > 8*1024*1024)
 669             fatal("Over max stack size for one thread\n");
 670         p->pTable->allocate(p->stack_min, PageBytes);
 671         warn("Increasing stack size by one page.");
 672     }
 673     // Otherwise, we have an unexpected page fault. Report that fact,
 674     // and what address was accessed to cause the fault.
 675     else
 676     {
 677         panic("Page table fault when accessing virtual address %#x\n", vaddr);
 678     }
 679 }
 680
 681 #endif
 682
 683 } // namespace SparcISA
 684