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34 #include "arch/sparc/faults.hh"
35 #include "arch/sparc/isa_traits.hh"
36 #include "arch/sparc/types.hh"
37 #include "base/bitfield.hh"
38 #include "base/trace.hh"
39 #include "config/full_system.hh"
40 #include "cpu/base.hh"
41 #include "cpu/thread_context.hh"
43 #include "arch/sparc/process.hh"
44 #include "mem/page_table.hh"
45 #include "sim/process.hh"
53 template<> SparcFaultBase::FaultVals
54 SparcFault
<PowerOnReset
>::vals
=
55 {"power_on_reset", 0x001, 0, {H
, H
, H
}};
57 template<> SparcFaultBase::FaultVals
58 SparcFault
<WatchDogReset
>::vals
=
59 {"watch_dog_reset", 0x002, 120, {H
, H
, H
}};
61 template<> SparcFaultBase::FaultVals
62 SparcFault
<ExternallyInitiatedReset
>::vals
=
63 {"externally_initiated_reset", 0x003, 110, {H
, H
, H
}};
65 template<> SparcFaultBase::FaultVals
66 SparcFault
<SoftwareInitiatedReset
>::vals
=
67 {"software_initiated_reset", 0x004, 130, {SH
, SH
, H
}};
69 template<> SparcFaultBase::FaultVals
70 SparcFault
<REDStateException
>::vals
=
71 {"RED_state_exception", 0x005, 1, {H
, H
, H
}};
73 template<> SparcFaultBase::FaultVals
74 SparcFault
<StoreError
>::vals
=
75 {"store_error", 0x007, 201, {H
, H
, H
}};
77 template<> SparcFaultBase::FaultVals
78 SparcFault
<InstructionAccessException
>::vals
=
79 {"instruction_access_exception", 0x008, 300, {H
, H
, H
}};
81 //XXX This trap is apparently dropped from ua2005
82 /*template<> SparcFaultBase::FaultVals
83 SparcFault<InstructionAccessMMUMiss>::vals =
84 {"inst_mmu", 0x009, 2, {H, H, H}};*/
86 template<> SparcFaultBase::FaultVals
87 SparcFault
<InstructionAccessError
>::vals
=
88 {"instruction_access_error", 0x00A, 400, {H
, H
, H
}};
90 template<> SparcFaultBase::FaultVals
91 SparcFault
<IllegalInstruction
>::vals
=
92 {"illegal_instruction", 0x010, 620, {H
, H
, H
}};
94 template<> SparcFaultBase::FaultVals
95 SparcFault
<PrivilegedOpcode
>::vals
=
96 {"privileged_opcode", 0x011, 700, {P
, SH
, SH
}};
98 //XXX This trap is apparently dropped from ua2005
99 /*template<> SparcFaultBase::FaultVals
100 SparcFault<UnimplementedLDD>::vals =
101 {"unimp_ldd", 0x012, 6, {H, H, H}};*/
103 //XXX This trap is apparently dropped from ua2005
104 /*template<> SparcFaultBase::FaultVals
105 SparcFault<UnimplementedSTD>::vals =
106 {"unimp_std", 0x013, 6, {H, H, H}};*/
108 template<> SparcFaultBase::FaultVals
109 SparcFault
<FpDisabled
>::vals
=
110 {"fp_disabled", 0x020, 800, {P
, P
, H
}};
112 template<> SparcFaultBase::FaultVals
113 SparcFault
<FpExceptionIEEE754
>::vals
=
114 {"fp_exception_ieee_754", 0x021, 1110, {P
, P
, H
}};
116 template<> SparcFaultBase::FaultVals
117 SparcFault
<FpExceptionOther
>::vals
=
118 {"fp_exception_other", 0x022, 1110, {P
, P
, H
}};
120 template<> SparcFaultBase::FaultVals
121 SparcFault
<TagOverflow
>::vals
=
122 {"tag_overflow", 0x023, 1400, {P
, P
, H
}};
124 template<> SparcFaultBase::FaultVals
125 SparcFault
<CleanWindow
>::vals
=
126 {"clean_window", 0x024, 1010, {P
, P
, H
}};
128 template<> SparcFaultBase::FaultVals
129 SparcFault
<DivisionByZero
>::vals
=
130 {"division_by_zero", 0x028, 1500, {P
, P
, H
}};
132 template<> SparcFaultBase::FaultVals
133 SparcFault
<InternalProcessorError
>::vals
=
134 {"internal_processor_error", 0x029, 4, {H
, H
, H
}};
136 template<> SparcFaultBase::FaultVals
137 SparcFault
<InstructionInvalidTSBEntry
>::vals
=
138 {"instruction_invalid_tsb_entry", 0x02A, 210, {H
, H
, SH
}};
140 template<> SparcFaultBase::FaultVals
141 SparcFault
<DataInvalidTSBEntry
>::vals
=
142 {"data_invalid_tsb_entry", 0x02B, 1203, {H
, H
, H
}};
144 template<> SparcFaultBase::FaultVals
145 SparcFault
<DataAccessException
>::vals
=
146 {"data_access_exception", 0x030, 1201, {H
, H
, H
}};
148 //XXX This trap is apparently dropped from ua2005
149 /*template<> SparcFaultBase::FaultVals
150 SparcFault<DataAccessMMUMiss>::vals =
151 {"data_mmu", 0x031, 12, {H, H, H}};*/
153 template<> SparcFaultBase::FaultVals
154 SparcFault
<DataAccessError
>::vals
=
155 {"data_access_error", 0x032, 1210, {H
, H
, H
}};
157 template<> SparcFaultBase::FaultVals
158 SparcFault
<DataAccessProtection
>::vals
=
159 {"data_access_protection", 0x033, 1207, {H
, H
, H
}};
161 template<> SparcFaultBase::FaultVals
162 SparcFault
<MemAddressNotAligned
>::vals
=
163 {"mem_address_not_aligned", 0x034, 1020, {H
, H
, H
}};
165 template<> SparcFaultBase::FaultVals
166 SparcFault
<LDDFMemAddressNotAligned
>::vals
=
167 {"LDDF_mem_address_not_aligned", 0x035, 1010, {H
, H
, H
}};
169 template<> SparcFaultBase::FaultVals
170 SparcFault
<STDFMemAddressNotAligned
>::vals
=
171 {"STDF_mem_address_not_aligned", 0x036, 1010, {H
, H
, H
}};
173 template<> SparcFaultBase::FaultVals
174 SparcFault
<PrivilegedAction
>::vals
=
175 {"privileged_action", 0x037, 1110, {H
, H
, SH
}};
177 template<> SparcFaultBase::FaultVals
178 SparcFault
<LDQFMemAddressNotAligned
>::vals
=
179 {"LDQF_mem_address_not_aligned", 0x038, 1010, {H
, H
, H
}};
181 template<> SparcFaultBase::FaultVals
182 SparcFault
<STQFMemAddressNotAligned
>::vals
=
183 {"STQF_mem_address_not_aligned", 0x039, 1010, {H
, H
, H
}};
185 template<> SparcFaultBase::FaultVals
186 SparcFault
<InstructionRealTranslationMiss
>::vals
=
187 {"instruction_real_translation_miss", 0x03E, 208, {H
, H
, SH
}};
189 template<> SparcFaultBase::FaultVals
190 SparcFault
<DataRealTranslationMiss
>::vals
=
191 {"data_real_translation_miss", 0x03F, 1203, {H
, H
, H
}};
193 //XXX This trap is apparently dropped from ua2005
194 /*template<> SparcFaultBase::FaultVals
195 SparcFault<AsyncDataError>::vals =
196 {"async_data", 0x040, 2, {H, H, H}};*/
198 template<> SparcFaultBase::FaultVals
199 SparcFault
<InterruptLevelN
>::vals
=
200 {"interrupt_level_n", 0x040, 0, {P
, P
, SH
}};
202 template<> SparcFaultBase::FaultVals
203 SparcFault
<HstickMatch
>::vals
=
204 {"hstick_match", 0x05E, 1601, {H
, H
, H
}};
206 template<> SparcFaultBase::FaultVals
207 SparcFault
<TrapLevelZero
>::vals
=
208 {"trap_level_zero", 0x05F, 202, {H
, H
, SH
}};
210 template<> SparcFaultBase::FaultVals
211 SparcFault
<InterruptVector
>::vals
=
212 {"interrupt_vector", 0x060, 2630, {H
, H
, H
}};
214 template<> SparcFaultBase::FaultVals
215 SparcFault
<PAWatchpoint
>::vals
=
216 {"PA_watchpoint", 0x061, 1209, {H
, H
, H
}};
218 template<> SparcFaultBase::FaultVals
219 SparcFault
<VAWatchpoint
>::vals
=
220 {"VA_watchpoint", 0x062, 1120, {P
, P
, SH
}};
222 template<> SparcFaultBase::FaultVals
223 SparcFault
<FastInstructionAccessMMUMiss
>::vals
=
224 {"fast_instruction_access_MMU_miss", 0x064, 208, {H
, H
, SH
}};
226 template<> SparcFaultBase::FaultVals
227 SparcFault
<FastDataAccessMMUMiss
>::vals
=
228 {"fast_data_access_MMU_miss", 0x068, 1203, {H
, H
, H
}};
230 template<> SparcFaultBase::FaultVals
231 SparcFault
<FastDataAccessProtection
>::vals
=
232 {"fast_data_access_protection", 0x06C, 1207, {H
, H
, H
}};
234 template<> SparcFaultBase::FaultVals
235 SparcFault
<InstructionBreakpoint
>::vals
=
236 {"instruction_break", 0x076, 610, {H
, H
, H
}};
238 template<> SparcFaultBase::FaultVals
239 SparcFault
<CpuMondo
>::vals
=
240 {"cpu_mondo", 0x07C, 1608, {P
, P
, SH
}};
242 template<> SparcFaultBase::FaultVals
243 SparcFault
<DevMondo
>::vals
=
244 {"dev_mondo", 0x07D, 1611, {P
, P
, SH
}};
246 template<> SparcFaultBase::FaultVals
247 SparcFault
<ResumableError
>::vals
=
248 {"resume_error", 0x07E, 3330, {P
, P
, SH
}};
250 template<> SparcFaultBase::FaultVals
251 SparcFault
<SpillNNormal
>::vals
=
252 {"spill_n_normal", 0x080, 900, {P
, P
, H
}};
254 template<> SparcFaultBase::FaultVals
255 SparcFault
<SpillNOther
>::vals
=
256 {"spill_n_other", 0x0A0, 900, {P
, P
, H
}};
258 template<> SparcFaultBase::FaultVals
259 SparcFault
<FillNNormal
>::vals
=
260 {"fill_n_normal", 0x0C0, 900, {P
, P
, H
}};
262 template<> SparcFaultBase::FaultVals
263 SparcFault
<FillNOther
>::vals
=
264 {"fill_n_other", 0x0E0, 900, {P
, P
, H
}};
266 template<> SparcFaultBase::FaultVals
267 SparcFault
<TrapInstruction
>::vals
=
268 {"trap_instruction", 0x100, 1602, {P
, P
, H
}};
271 template<> SparcFaultBase::FaultVals
272 SparcFault
<PageTableFault
>::vals
=
273 {"page_table_fault", 0x0000, 0, {SH
, SH
, SH
}};
277 * This causes the thread context to enter RED state. This causes the side
278 * effects which go with entering RED state because of a trap.
281 void enterREDState(ThreadContext
*tc
)
283 //@todo Disable the mmu?
284 //@todo Disable watchpoints?
285 MiscReg HPSTATE
= tc
->readMiscRegNoEffect(MISCREG_HPSTATE
);
290 tc
->setMiscReg(MISCREG_HPSTATE
, HPSTATE
);
291 //PSTATE.priv is set to 1 here. The manual says it should be 0, but
292 //Legion sets it to 1.
293 MiscReg PSTATE
= tc
->readMiscRegNoEffect(MISCREG_PSTATE
);
295 tc
->setMiscReg(MISCREG_PSTATE
, PSTATE
);
299 * This sets everything up for a RED state trap except for actually jumping to
303 void doREDFault(ThreadContext
*tc
, TrapType tt
)
305 MiscReg TL
= tc
->readMiscRegNoEffect(MISCREG_TL
);
306 MiscReg TSTATE
= tc
->readMiscRegNoEffect(MISCREG_TSTATE
);
307 MiscReg PSTATE
= tc
->readMiscRegNoEffect(MISCREG_PSTATE
);
308 MiscReg HPSTATE
= tc
->readMiscRegNoEffect(MISCREG_HPSTATE
);
309 //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR);
310 MiscReg CCR
= tc
->readIntReg(NumIntArchRegs
+ 2);
311 MiscReg ASI
= tc
->readMiscRegNoEffect(MISCREG_ASI
);
312 MiscReg CWP
= tc
->readMiscRegNoEffect(MISCREG_CWP
);
313 //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE);
314 MiscReg CANSAVE
= tc
->readMiscRegNoEffect(NumIntArchRegs
+ 3);
315 MiscReg GL
= tc
->readMiscRegNoEffect(MISCREG_GL
);
316 MiscReg PC
= tc
->readPC();
317 MiscReg NPC
= tc
->readNextPC();
321 if (bits(PSTATE
, 3,3)) {
326 //set TSTATE.gl to gl
327 replaceBits(TSTATE
, 42, 40, GL
);
328 //set TSTATE.ccr to ccr
329 replaceBits(TSTATE
, 39, 32, CCR
);
330 //set TSTATE.asi to asi
331 replaceBits(TSTATE
, 31, 24, ASI
);
332 //set TSTATE.pstate to pstate
333 replaceBits(TSTATE
, 20, 8, PSTATE
);
334 //set TSTATE.cwp to cwp
335 replaceBits(TSTATE
, 4, 0, CWP
);
338 tc
->setMiscRegNoEffect(MISCREG_TSTATE
, TSTATE
);
341 tc
->setMiscRegNoEffect(MISCREG_TPC
, PC
);
343 tc
->setMiscRegNoEffect(MISCREG_TNPC
, NPC
);
345 //set HTSTATE.hpstate to hpstate
346 tc
->setMiscRegNoEffect(MISCREG_HTSTATE
, HPSTATE
);
349 tc
->setMiscRegNoEffect(MISCREG_TT
, tt
);
352 tc
->setMiscReg(MISCREG_GL
, min
<int>(GL
+1, MaxGL
));
354 PSTATE
= mbits(PSTATE
, 2, 2); // just save the priv bit
355 PSTATE
|= (1 << 4); //set PSTATE.pef to 1
356 tc
->setMiscRegNoEffect(MISCREG_PSTATE
, PSTATE
);
358 //set HPSTATE.red to 1
360 //set HPSTATE.hpriv to 1
362 //set HPSTATE.ibe to 0
363 HPSTATE
&= ~(1 << 10);
364 //set HPSTATE.tlz to 0
365 HPSTATE
&= ~(1 << 0);
366 tc
->setMiscRegNoEffect(MISCREG_HPSTATE
, HPSTATE
);
368 bool changedCWP
= true;
371 else if(0x80 <= tt
&& tt
<= 0xbf)
372 CWP
+= (CANSAVE
+ 2);
373 else if(0xc0 <= tt
&& tt
<= 0xff)
380 CWP
= (CWP
+ NWindows
) % NWindows
;
381 tc
->setMiscReg(MISCREG_CWP
, CWP
);
386 * This sets everything up for a normal trap except for actually jumping to
390 void doNormalFault(ThreadContext
*tc
, TrapType tt
, bool gotoHpriv
)
392 MiscReg TL
= tc
->readMiscRegNoEffect(MISCREG_TL
);
393 MiscReg TSTATE
= tc
->readMiscRegNoEffect(MISCREG_TSTATE
);
394 MiscReg PSTATE
= tc
->readMiscRegNoEffect(MISCREG_PSTATE
);
395 MiscReg HPSTATE
= tc
->readMiscRegNoEffect(MISCREG_HPSTATE
);
396 //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR);
397 MiscReg CCR
= tc
->readIntReg(NumIntArchRegs
+ 2);
398 MiscReg ASI
= tc
->readMiscRegNoEffect(MISCREG_ASI
);
399 MiscReg CWP
= tc
->readMiscRegNoEffect(MISCREG_CWP
);
400 //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE);
401 MiscReg CANSAVE
= tc
->readIntReg(NumIntArchRegs
+ 3);
402 MiscReg GL
= tc
->readMiscRegNoEffect(MISCREG_GL
);
403 MiscReg PC
= tc
->readPC();
404 MiscReg NPC
= tc
->readNextPC();
406 if (bits(PSTATE
, 3,3)) {
411 //Increment the trap level
413 tc
->setMiscRegNoEffect(MISCREG_TL
, TL
);
417 //set TSTATE.gl to gl
418 replaceBits(TSTATE
, 42, 40, GL
);
419 //set TSTATE.ccr to ccr
420 replaceBits(TSTATE
, 39, 32, CCR
);
421 //set TSTATE.asi to asi
422 replaceBits(TSTATE
, 31, 24, ASI
);
423 //set TSTATE.pstate to pstate
424 replaceBits(TSTATE
, 20, 8, PSTATE
);
425 //set TSTATE.cwp to cwp
426 replaceBits(TSTATE
, 4, 0, CWP
);
429 tc
->setMiscRegNoEffect(MISCREG_TSTATE
, TSTATE
);
432 tc
->setMiscRegNoEffect(MISCREG_TPC
, PC
);
434 tc
->setMiscRegNoEffect(MISCREG_TNPC
, NPC
);
436 //set HTSTATE.hpstate to hpstate
437 tc
->setMiscRegNoEffect(MISCREG_HTSTATE
, HPSTATE
);
440 tc
->setMiscRegNoEffect(MISCREG_TT
, tt
);
442 //Update the global register level
444 tc
->setMiscReg(MISCREG_GL
, min
<int>(GL
+1, MaxPGL
));
446 tc
->setMiscReg(MISCREG_GL
, min
<int>(GL
+1, MaxGL
));
448 //PSTATE.mm is unchanged
449 PSTATE
|= (1 << 4); //PSTATE.pef = whether or not an fpu is present
450 PSTATE
&= ~(1 << 3); //PSTATE.am = 0
451 PSTATE
&= ~(1 << 1); //PSTATE.ie = 0
452 //PSTATE.tle is unchanged
457 PSTATE
&= ~(1 << 9); // PSTATE.cle = 0
458 //The manual says PSTATE.priv should be 0, but Legion leaves it alone
459 HPSTATE
&= ~(1 << 5); //HPSTATE.red = 0
460 HPSTATE
|= (1 << 2); //HPSTATE.hpriv = 1
461 HPSTATE
&= ~(1 << 10); //HPSTATE.ibe = 0
462 //HPSTATE.tlz is unchanged
463 tc
->setMiscRegNoEffect(MISCREG_HPSTATE
, HPSTATE
);
464 } else { // we are going to priv
465 PSTATE
|= (1 << 2); //PSTATE.priv = 1
466 replaceBits(PSTATE
, 9, 9, PSTATE
>> 8); //PSTATE.cle = PSTATE.tle
468 tc
->setMiscRegNoEffect(MISCREG_PSTATE
, PSTATE
);
471 bool changedCWP
= true;
474 else if (0x80 <= tt
&& tt
<= 0xbf)
475 CWP
+= (CANSAVE
+ 2);
476 else if (0xc0 <= tt
&& tt
<= 0xff)
483 CWP
= (CWP
+ NWindows
) % NWindows
;
484 tc
->setMiscReg(MISCREG_CWP
, CWP
);
488 void getREDVector(MiscReg TT
, Addr
& PC
, Addr
& NPC
)
490 //XXX The following constant might belong in a header file.
491 const Addr RSTVAddr
= 0xFFF0000000ULL
;
492 PC
= RSTVAddr
| ((TT
<< 5) & 0xFF);
493 NPC
= PC
+ sizeof(MachInst
);
496 void getHyperVector(ThreadContext
* tc
, Addr
& PC
, Addr
& NPC
, MiscReg TT
)
498 Addr HTBA
= tc
->readMiscRegNoEffect(MISCREG_HTBA
);
499 PC
= (HTBA
& ~mask(14)) | ((TT
<< 5) & mask(14));
500 NPC
= PC
+ sizeof(MachInst
);
503 void getPrivVector(ThreadContext
* tc
, Addr
& PC
, Addr
& NPC
, MiscReg TT
, MiscReg TL
)
505 Addr TBA
= tc
->readMiscRegNoEffect(MISCREG_TBA
);
506 PC
= (TBA
& ~mask(15)) |
507 (TL
> 1 ? (1 << 14) : 0) |
508 ((TT
<< 5) & mask(14));
509 NPC
= PC
+ sizeof(MachInst
);
514 void SparcFaultBase::invoke(ThreadContext
* tc
)
516 //panic("Invoking a second fault!\n");
517 FaultBase::invoke(tc
);
520 //We can refer to this to see what the trap level -was-, but something
521 //in the middle could change it in the regfile out from under us.
522 MiscReg tl
= tc
->readMiscRegNoEffect(MISCREG_TL
);
523 MiscReg tt
= tc
->readMiscRegNoEffect(MISCREG_TT
);
524 MiscReg pstate
= tc
->readMiscRegNoEffect(MISCREG_PSTATE
);
525 MiscReg hpstate
= tc
->readMiscRegNoEffect(MISCREG_HPSTATE
);
529 PrivilegeLevel current
;
530 if (hpstate
& HPSTATE::hpriv
)
531 current
= Hyperprivileged
;
532 else if (pstate
& PSTATE::priv
)
533 current
= Privileged
;
537 PrivilegeLevel level
= getNextLevel(current
);
539 if ((hpstate
& HPSTATE::red
) || (tl
== MaxTL
- 1)) {
540 getREDVector(5, PC
, NPC
);
542 //This changes the hpstate and pstate, so we need to make sure we
543 //save the old version on the trap stack in doREDFault.
545 } else if (tl
== MaxTL
) {
546 panic("Should go to error state here.. crap\n");
547 //Do error_state somehow?
548 //Probably inject a WDR fault using the interrupt mechanism.
549 //What should the PC and NPC be set to?
550 } else if (tl
> MaxPTL
&& level
== Privileged
) {
551 //guest_watchdog fault
552 doNormalFault(tc
, trapType(), true);
553 getHyperVector(tc
, PC
, NPC
, 2);
554 } else if (level
== Hyperprivileged
||
555 level
== Privileged
&& trapType() >= 384) {
556 doNormalFault(tc
, trapType(), true);
557 getHyperVector(tc
, PC
, NPC
, trapType());
559 doNormalFault(tc
, trapType(), false);
560 getPrivVector(tc
, PC
, NPC
, trapType(), tl
+1);
565 tc
->setNextNPC(NPC
+ sizeof(MachInst
));
568 void PowerOnReset::invoke(ThreadContext
* tc
)
570 //For SPARC, when a system is first started, there is a power
571 //on reset Trap which sets the processor into the following state.
572 //Bits that aren't set aren't defined on startup.
574 tc
->setMiscRegNoEffect(MISCREG_TL
, MaxTL
);
575 tc
->setMiscRegNoEffect(MISCREG_TT
, trapType());
576 tc
->setMiscReg(MISCREG_GL
, MaxGL
);
578 //Turn on pef and priv, set everything else to 0
579 tc
->setMiscRegNoEffect(MISCREG_PSTATE
, (1 << 4) | (1 << 2));
581 //Turn on red and hpriv, set everything else to 0
582 MiscReg HPSTATE
= tc
->readMiscRegNoEffect(MISCREG_HPSTATE
);
588 HPSTATE
&= ~(1 << 10);
590 HPSTATE
&= ~(1 << 0);
591 tc
->setMiscRegNoEffect(MISCREG_HPSTATE
, HPSTATE
);
593 //The tick register is unreadable by nonprivileged software
594 tc
->setMiscRegNoEffect(MISCREG_TICK
, 1ULL << 63);
596 //Enter RED state. We do this last so that the actual state preserved in
597 //the trap stack is the state from before this fault.
601 getREDVector(trapType(), PC
, NPC
);
604 tc
->setNextNPC(NPC
+ sizeof(MachInst
));
606 //These registers are specified as "undefined" after a POR, and they
607 //should have reasonable values after the miscregfile is reset
609 // Clear all the soft interrupt bits
611 // disable timer compare interrupts, reset tick_cmpr
612 tc->setMiscRegNoEffect(MISCREG_
613 tick_cmprFields.int_dis = 1;
614 tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
615 stickFields.npt = 1; //The TICK register is unreadable by by !priv
616 stick_cmprFields.int_dis = 1; // disable timer compare interrupts
617 stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
621 hintp = 0; // no interrupts pending
622 hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
623 hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
627 #else // !FULL_SYSTEM
629 void SpillNNormal::invoke(ThreadContext
*tc
)
631 doNormalFault(tc
, trapType(), false);
633 Process
*p
= tc
->getProcessPtr();
635 //XXX This will only work in faults from a SparcLiveProcess
636 SparcLiveProcess
*lp
= dynamic_cast<SparcLiveProcess
*>(p
);
639 //Then adjust the PC and NPC
640 Addr spillStart
= lp
->readSpillStart();
641 tc
->setPC(spillStart
);
642 tc
->setNextPC(spillStart
+ sizeof(MachInst
));
643 tc
->setNextNPC(spillStart
+ 2*sizeof(MachInst
));
646 void FillNNormal::invoke(ThreadContext
*tc
)
648 doNormalFault(tc
, trapType(), false);
650 Process
* p
= tc
->getProcessPtr();
652 //XXX This will only work in faults from a SparcLiveProcess
653 SparcLiveProcess
*lp
= dynamic_cast<SparcLiveProcess
*>(p
);
656 //Then adjust the PC and NPC
657 Addr fillStart
= lp
->readFillStart();
658 tc
->setPC(fillStart
);
659 tc
->setNextPC(fillStart
+ sizeof(MachInst
));
660 tc
->setNextNPC(fillStart
+ 2*sizeof(MachInst
));
663 void TrapInstruction::invoke(ThreadContext
*tc
)
665 //In SE, this mechanism is how the process requests a service from the
666 //operating system. We'll get the process object from the thread context
667 //and let it service the request.
669 Process
*p
= tc
->getProcessPtr();
671 SparcLiveProcess
*lp
= dynamic_cast<SparcLiveProcess
*>(p
);
674 lp
->handleTrap(_n
, tc
);
676 //We need to explicitly advance the pc, since that's not done for us
677 //on a faulting instruction
678 tc
->setPC(tc
->readNextPC());
679 tc
->setNextPC(tc
->readNextNPC());
680 tc
->setNextNPC(tc
->readNextNPC() + sizeof(MachInst
));
683 void PageTableFault::invoke(ThreadContext
*tc
)
685 Process
*p
= tc
->getProcessPtr();
687 // We've accessed the next page of the stack, so extend the stack
689 if(vaddr
< p
->stack_min
&& vaddr
>= p
->stack_min
- PageBytes
)
691 p
->stack_min
-= PageBytes
;
692 if(p
->stack_base
- p
->stack_min
> 8*1024*1024)
693 fatal("Over max stack size for one thread\n");
694 p
->pTable
->allocate(p
->stack_min
, PageBytes
);
695 warn("Increasing stack size by one page.");
697 // Otherwise, we have an unexpected page fault. Report that fact,
698 // and what address was accessed to cause the fault.
701 panic("Page table fault when accessing virtual address %#x\n", vaddr
);
707 } // namespace SparcISA