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34 #include "arch/sparc/faults.hh"
35 #include "arch/sparc/isa_traits.hh"
36 #include "arch/sparc/types.hh"
37 #include "base/bitfield.hh"
38 #include "base/trace.hh"
39 #include "config/full_system.hh"
40 #include "cpu/base.hh"
41 #include "cpu/thread_context.hh"
43 #include "arch/sparc/process.hh"
44 #include "mem/page_table.hh"
45 #include "sim/process.hh"
53 template<> SparcFaultBase::FaultVals
54 SparcFault
<PowerOnReset
>::vals
=
55 {"power_on_reset", 0x001, 0, {H
, H
, H
}};
57 template<> SparcFaultBase::FaultVals
58 SparcFault
<WatchDogReset
>::vals
=
59 {"watch_dog_reset", 0x002, 120, {H
, H
, H
}};
61 template<> SparcFaultBase::FaultVals
62 SparcFault
<ExternallyInitiatedReset
>::vals
=
63 {"externally_initiated_reset", 0x003, 110, {H
, H
, H
}};
65 template<> SparcFaultBase::FaultVals
66 SparcFault
<SoftwareInitiatedReset
>::vals
=
67 {"software_initiated_reset", 0x004, 130, {SH
, SH
, H
}};
69 template<> SparcFaultBase::FaultVals
70 SparcFault
<REDStateException
>::vals
=
71 {"RED_state_exception", 0x005, 1, {H
, H
, H
}};
73 template<> SparcFaultBase::FaultVals
74 SparcFault
<StoreError
>::vals
=
75 {"store_error", 0x007, 201, {H
, H
, H
}};
77 template<> SparcFaultBase::FaultVals
78 SparcFault
<InstructionAccessException
>::vals
=
79 {"instruction_access_exception", 0x008, 300, {H
, H
, H
}};
81 //XXX This trap is apparently dropped from ua2005
82 /*template<> SparcFaultBase::FaultVals
83 SparcFault<InstructionAccessMMUMiss>::vals =
84 {"inst_mmu", 0x009, 2, {H, H, H}};*/
86 template<> SparcFaultBase::FaultVals
87 SparcFault
<InstructionAccessError
>::vals
=
88 {"instruction_access_error", 0x00A, 400, {H
, H
, H
}};
90 template<> SparcFaultBase::FaultVals
91 SparcFault
<IllegalInstruction
>::vals
=
92 {"illegal_instruction", 0x010, 620, {H
, H
, H
}};
94 template<> SparcFaultBase::FaultVals
95 SparcFault
<PrivilegedOpcode
>::vals
=
96 {"privileged_opcode", 0x011, 700, {P
, SH
, SH
}};
98 //XXX This trap is apparently dropped from ua2005
99 /*template<> SparcFaultBase::FaultVals
100 SparcFault<UnimplementedLDD>::vals =
101 {"unimp_ldd", 0x012, 6, {H, H, H}};*/
103 //XXX This trap is apparently dropped from ua2005
104 /*template<> SparcFaultBase::FaultVals
105 SparcFault<UnimplementedSTD>::vals =
106 {"unimp_std", 0x013, 6, {H, H, H}};*/
108 template<> SparcFaultBase::FaultVals
109 SparcFault
<FpDisabled
>::vals
=
110 {"fp_disabled", 0x020, 800, {P
, P
, H
}};
112 template<> SparcFaultBase::FaultVals
113 SparcFault
<FpExceptionIEEE754
>::vals
=
114 {"fp_exception_ieee_754", 0x021, 1110, {P
, P
, H
}};
116 template<> SparcFaultBase::FaultVals
117 SparcFault
<FpExceptionOther
>::vals
=
118 {"fp_exception_other", 0x022, 1110, {P
, P
, H
}};
120 template<> SparcFaultBase::FaultVals
121 SparcFault
<TagOverflow
>::vals
=
122 {"tag_overflow", 0x023, 1400, {P
, P
, H
}};
124 template<> SparcFaultBase::FaultVals
125 SparcFault
<CleanWindow
>::vals
=
126 {"clean_window", 0x024, 1010, {P
, P
, H
}};
128 template<> SparcFaultBase::FaultVals
129 SparcFault
<DivisionByZero
>::vals
=
130 {"division_by_zero", 0x028, 1500, {P
, P
, H
}};
132 template<> SparcFaultBase::FaultVals
133 SparcFault
<InternalProcessorError
>::vals
=
134 {"internal_processor_error", 0x029, 4, {H
, H
, H
}};
136 template<> SparcFaultBase::FaultVals
137 SparcFault
<InstructionInvalidTSBEntry
>::vals
=
138 {"instruction_invalid_tsb_entry", 0x02A, 210, {H
, H
, SH
}};
140 template<> SparcFaultBase::FaultVals
141 SparcFault
<DataInvalidTSBEntry
>::vals
=
142 {"data_invalid_tsb_entry", 0x02B, 1203, {H
, H
, H
}};
144 template<> SparcFaultBase::FaultVals
145 SparcFault
<DataAccessException
>::vals
=
146 {"data_access_exception", 0x030, 1201, {H
, H
, H
}};
148 //XXX This trap is apparently dropped from ua2005
149 /*template<> SparcFaultBase::FaultVals
150 SparcFault<DataAccessMMUMiss>::vals =
151 {"data_mmu", 0x031, 12, {H, H, H}};*/
153 template<> SparcFaultBase::FaultVals
154 SparcFault
<DataAccessError
>::vals
=
155 {"data_access_error", 0x032, 1210, {H
, H
, H
}};
157 template<> SparcFaultBase::FaultVals
158 SparcFault
<DataAccessProtection
>::vals
=
159 {"data_access_protection", 0x033, 1207, {H
, H
, H
}};
161 template<> SparcFaultBase::FaultVals
162 SparcFault
<MemAddressNotAligned
>::vals
=
163 {"mem_address_not_aligned", 0x034, 1020, {H
, H
, H
}};
165 template<> SparcFaultBase::FaultVals
166 SparcFault
<LDDFMemAddressNotAligned
>::vals
=
167 {"LDDF_mem_address_not_aligned", 0x035, 1010, {H
, H
, H
}};
169 template<> SparcFaultBase::FaultVals
170 SparcFault
<STDFMemAddressNotAligned
>::vals
=
171 {"STDF_mem_address_not_aligned", 0x036, 1010, {H
, H
, H
}};
173 template<> SparcFaultBase::FaultVals
174 SparcFault
<PrivilegedAction
>::vals
=
175 {"privileged_action", 0x037, 1110, {H
, H
, SH
}};
177 template<> SparcFaultBase::FaultVals
178 SparcFault
<LDQFMemAddressNotAligned
>::vals
=
179 {"LDQF_mem_address_not_aligned", 0x038, 1010, {H
, H
, H
}};
181 template<> SparcFaultBase::FaultVals
182 SparcFault
<STQFMemAddressNotAligned
>::vals
=
183 {"STQF_mem_address_not_aligned", 0x039, 1010, {H
, H
, H
}};
185 template<> SparcFaultBase::FaultVals
186 SparcFault
<InstructionRealTranslationMiss
>::vals
=
187 {"instruction_real_translation_miss", 0x03E, 208, {H
, H
, SH
}};
189 template<> SparcFaultBase::FaultVals
190 SparcFault
<DataRealTranslationMiss
>::vals
=
191 {"data_real_translation_miss", 0x03F, 1203, {H
, H
, H
}};
193 //XXX This trap is apparently dropped from ua2005
194 /*template<> SparcFaultBase::FaultVals
195 SparcFault<AsyncDataError>::vals =
196 {"async_data", 0x040, 2, {H, H, H}};*/
198 template<> SparcFaultBase::FaultVals
199 SparcFault
<InterruptLevelN
>::vals
=
200 {"interrupt_level_n", 0x041, 0, {P
, P
, SH
}};
202 template<> SparcFaultBase::FaultVals
203 SparcFault
<HstickMatch
>::vals
=
204 {"hstick_match", 0x05E, 1601, {H
, H
, H
}};
206 template<> SparcFaultBase::FaultVals
207 SparcFault
<TrapLevelZero
>::vals
=
208 {"trap_level_zero", 0x05F, 202, {H
, H
, SH
}};
210 template<> SparcFaultBase::FaultVals
211 SparcFault
<PAWatchpoint
>::vals
=
212 {"PA_watchpoint", 0x061, 1209, {H
, H
, H
}};
214 template<> SparcFaultBase::FaultVals
215 SparcFault
<VAWatchpoint
>::vals
=
216 {"VA_watchpoint", 0x062, 1120, {P
, P
, SH
}};
218 template<> SparcFaultBase::FaultVals
219 SparcFault
<FastInstructionAccessMMUMiss
>::vals
=
220 {"fast_instruction_access_MMU_miss", 0x064, 208, {H
, H
, SH
}};
222 template<> SparcFaultBase::FaultVals
223 SparcFault
<FastDataAccessMMUMiss
>::vals
=
224 {"fast_data_access_MMU_miss", 0x068, 1203, {H
, H
, H
}};
226 template<> SparcFaultBase::FaultVals
227 SparcFault
<FastDataAccessProtection
>::vals
=
228 {"fast_data_access_protection", 0x06C, 1207, {H
, H
, H
}};
230 template<> SparcFaultBase::FaultVals
231 SparcFault
<InstructionBreakpoint
>::vals
=
232 {"instruction_break", 0x076, 610, {H
, H
, H
}};
234 template<> SparcFaultBase::FaultVals
235 SparcFault
<CpuMondo
>::vals
=
236 {"cpu_mondo", 0x07C, 1608, {P
, P
, SH
}};
238 template<> SparcFaultBase::FaultVals
239 SparcFault
<DevMondo
>::vals
=
240 {"dev_mondo", 0x07D, 1611, {P
, P
, SH
}};
242 template<> SparcFaultBase::FaultVals
243 SparcFault
<ResumeableError
>::vals
=
244 {"resume_error", 0x07E, 3330, {P
, P
, SH
}};
246 template<> SparcFaultBase::FaultVals
247 SparcFault
<SpillNNormal
>::vals
=
248 {"spill_n_normal", 0x080, 900, {P
, P
, H
}};
250 template<> SparcFaultBase::FaultVals
251 SparcFault
<SpillNOther
>::vals
=
252 {"spill_n_other", 0x0A0, 900, {P
, P
, H
}};
254 template<> SparcFaultBase::FaultVals
255 SparcFault
<FillNNormal
>::vals
=
256 {"fill_n_normal", 0x0C0, 900, {P
, P
, H
}};
258 template<> SparcFaultBase::FaultVals
259 SparcFault
<FillNOther
>::vals
=
260 {"fill_n_other", 0x0E0, 900, {P
, P
, H
}};
262 template<> SparcFaultBase::FaultVals
263 SparcFault
<TrapInstruction
>::vals
=
264 {"trap_instruction", 0x100, 1602, {P
, P
, H
}};
267 template<> SparcFaultBase::FaultVals
268 SparcFault
<PageTableFault
>::vals
=
269 {"page_table_fault", 0x0000, 0, {SH
, SH
, SH
}};
273 * This causes the thread context to enter RED state. This causes the side
274 * effects which go with entering RED state because of a trap.
277 void enterREDState(ThreadContext
*tc
)
279 //@todo Disable the mmu?
280 //@todo Disable watchpoints?
281 MiscReg HPSTATE
= tc
->readMiscReg(MISCREG_HPSTATE
);
286 tc
->setMiscReg(MISCREG_HPSTATE
, HPSTATE
);
290 * This sets everything up for a RED state trap except for actually jumping to
294 void doREDFault(ThreadContext
*tc
, TrapType tt
)
296 MiscReg TL
= tc
->readMiscReg(MISCREG_TL
);
297 MiscReg TSTATE
= tc
->readMiscReg(MISCREG_TSTATE
);
298 MiscReg PSTATE
= tc
->readMiscReg(MISCREG_PSTATE
);
299 MiscReg HPSTATE
= tc
->readMiscReg(MISCREG_HPSTATE
);
300 MiscReg CCR
= tc
->readMiscReg(MISCREG_CCR
);
301 MiscReg ASI
= tc
->readMiscReg(MISCREG_ASI
);
302 MiscReg CWP
= tc
->readMiscReg(MISCREG_CWP
);
303 MiscReg CANSAVE
= tc
->readMiscReg(MISCREG_CANSAVE
);
304 MiscReg GL
= tc
->readMiscReg(MISCREG_GL
);
305 MiscReg PC
= tc
->readPC();
306 MiscReg NPC
= tc
->readNextPC();
310 //set TSTATE.gl to gl
311 replaceBits(TSTATE
, 42, 40, GL
);
312 //set TSTATE.ccr to ccr
313 replaceBits(TSTATE
, 39, 32, CCR
);
314 //set TSTATE.asi to asi
315 replaceBits(TSTATE
, 31, 24, ASI
);
316 //set TSTATE.pstate to pstate
317 replaceBits(TSTATE
, 20, 8, PSTATE
);
318 //set TSTATE.cwp to cwp
319 replaceBits(TSTATE
, 4, 0, CWP
);
322 tc
->setMiscReg(MISCREG_TSTATE
, TSTATE
);
325 tc
->setMiscReg(MISCREG_TPC
, PC
);
327 tc
->setMiscReg(MISCREG_TNPC
, NPC
);
329 //set HTSTATE.hpstate to hpstate
330 tc
->setMiscReg(MISCREG_HTSTATE
, HPSTATE
);
333 tc
->setMiscReg(MISCREG_TT
, tt
);
336 tc
->setMiscRegWithEffect(MISCREG_GL
, min
<int>(GL
+1, MaxGL
));
338 //set PSTATE.mm to 00
339 //set PSTATE.pef to 1
343 //set PSTATE.priv to 0
347 //set PSTATE.cle to 0
349 //PSTATE.tle is unchanged
350 //XXX Where is the tct bit?
351 //set PSTATE.tct to 0
352 tc
->setMiscReg(MISCREG_PSTATE
, PSTATE
);
354 //set HPSTATE.red to 1
356 //set HPSTATE.hpriv to 1
358 //set HPSTATE.ibe to 0
359 HPSTATE
&= ~(1 << 10);
360 //set HPSTATE.tlz to 0
361 HPSTATE
&= ~(1 << 0);
362 tc
->setMiscReg(MISCREG_HPSTATE
, HPSTATE
);
364 bool changedCWP
= true;
367 else if(0x80 <= tt
&& tt
<= 0xbf)
368 CWP
+= (CANSAVE
+ 2);
369 else if(0xc0 <= tt
&& tt
<= 0xff)
376 CWP
= (CWP
+ NWindows
) % NWindows
;
377 tc
->setMiscRegWithEffect(MISCREG_CWP
, CWP
);
382 * This sets everything up for a normal trap except for actually jumping to
386 void doNormalFault(ThreadContext
*tc
, TrapType tt
, bool gotoHpriv
)
388 MiscReg TL
= tc
->readMiscReg(MISCREG_TL
);
389 MiscReg TSTATE
= tc
->readMiscReg(MISCREG_TSTATE
);
390 MiscReg PSTATE
= tc
->readMiscReg(MISCREG_PSTATE
);
391 MiscReg HPSTATE
= tc
->readMiscReg(MISCREG_HPSTATE
);
392 MiscReg CCR
= tc
->readMiscReg(MISCREG_CCR
);
393 MiscReg ASI
= tc
->readMiscReg(MISCREG_ASI
);
394 MiscReg CWP
= tc
->readMiscReg(MISCREG_CWP
);
395 MiscReg CANSAVE
= tc
->readMiscReg(MISCREG_CANSAVE
);
396 MiscReg GL
= tc
->readMiscReg(MISCREG_GL
);
397 MiscReg PC
= tc
->readPC();
398 MiscReg NPC
= tc
->readNextPC();
400 //Increment the trap level
402 tc
->setMiscReg(MISCREG_TL
, TL
);
406 //set TSTATE.gl to gl
407 replaceBits(TSTATE
, 42, 40, GL
);
408 //set TSTATE.ccr to ccr
409 replaceBits(TSTATE
, 39, 32, CCR
);
410 //set TSTATE.asi to asi
411 replaceBits(TSTATE
, 31, 24, ASI
);
412 //set TSTATE.pstate to pstate
413 replaceBits(TSTATE
, 20, 8, PSTATE
);
414 //set TSTATE.cwp to cwp
415 replaceBits(TSTATE
, 4, 0, CWP
);
418 tc
->setMiscReg(MISCREG_TSTATE
, TSTATE
);
421 tc
->setMiscReg(MISCREG_TPC
, PC
);
423 tc
->setMiscReg(MISCREG_TNPC
, NPC
);
425 //set HTSTATE.hpstate to hpstate
426 tc
->setMiscReg(MISCREG_HTSTATE
, HPSTATE
);
429 tc
->setMiscReg(MISCREG_TT
, tt
);
431 //Update the global register level
433 tc
->setMiscRegWithEffect(MISCREG_GL
, min
<int>(GL
+1, MaxPGL
));
435 tc
->setMiscRegWithEffect(MISCREG_GL
, min
<int>(GL
+1, MaxGL
));
437 //PSTATE.mm is unchanged
438 //PSTATE.pef = whether or not an fpu is present
439 //XXX We'll say there's one present, even though there aren't
440 //implementations for a decent number of the instructions
448 //PSTATE.cle = PSTATE.tle
449 replaceBits(PSTATE
, 9, 9, PSTATE
>> 8);
460 //PSTATE.tle is unchanged
462 //XXX Where exactly is this field?
463 tc
->setMiscReg(MISCREG_PSTATE
, PSTATE
);
468 HPSTATE
&= ~(1 << 5);
472 HPSTATE
&= ~(1 << 10);
473 //HPSTATE.tlz is unchanged
474 tc
->setMiscReg(MISCREG_HPSTATE
, HPSTATE
);
477 bool changedCWP
= true;
480 else if(0x80 <= tt
&& tt
<= 0xbf)
481 CWP
+= (CANSAVE
+ 2);
482 else if(0xc0 <= tt
&& tt
<= 0xff)
489 CWP
= (CWP
+ NWindows
) % NWindows
;
490 tc
->setMiscRegWithEffect(MISCREG_CWP
, CWP
);
494 void getREDVector(Addr
& PC
, Addr
& NPC
)
496 //XXX The following constant might belong in a header file.
497 const Addr RSTVAddr
= 0xFFFFFFFFF0000000ULL
;
498 PC
= RSTVAddr
| 0xA0;
499 NPC
= PC
+ sizeof(MachInst
);
502 void getHyperVector(ThreadContext
* tc
, Addr
& PC
, Addr
& NPC
, MiscReg TT
)
504 Addr HTBA
= tc
->readMiscReg(MISCREG_HTBA
);
505 PC
= (HTBA
& ~mask(14)) | ((TT
<< 5) & mask(14));
506 NPC
= PC
+ sizeof(MachInst
);
509 void getPrivVector(ThreadContext
* tc
, Addr
& PC
, Addr
& NPC
, MiscReg TT
, MiscReg TL
)
511 Addr TBA
= tc
->readMiscReg(MISCREG_TBA
);
512 PC
= (TBA
& ~mask(15)) |
513 (TL
> 1 ? (1 << 14) : 0) |
514 ((TT
<< 5) & mask(14));
515 NPC
= PC
+ sizeof(MachInst
);
520 void SparcFaultBase::invoke(ThreadContext
* tc
)
522 FaultBase::invoke(tc
);
525 //We can refer to this to see what the trap level -was-, but something
526 //in the middle could change it in the regfile out from under us.
527 MiscReg TL
= tc
->readMiscReg(MISCREG_TL
);
528 MiscReg TT
= tc
->readMiscReg(MISCREG_TT
);
529 MiscReg PSTATE
= tc
->readMiscReg(MISCREG_PSTATE
);
530 MiscReg HPSTATE
= tc
->readMiscReg(MISCREG_HPSTATE
);
534 PrivilegeLevel current
;
535 if(!(PSTATE
& (1 << 2)))
537 else if(!(HPSTATE
& (1 << 2)))
538 current
= Privileged
;
540 current
= Hyperprivileged
;
542 PrivilegeLevel level
= getNextLevel(current
);
544 if(HPSTATE
& (1 << 5) || TL
== MaxTL
- 1)
546 getREDVector(PC
, NPC
);
552 //Do error_state somehow?
553 //Probably inject a WDR fault using the interrupt mechanism.
554 //What should the PC and NPC be set to?
556 else if(TL
> MaxPTL
&& level
== Privileged
)
558 //guest_watchdog fault
559 doNormalFault(tc
, trapType(), true);
560 getHyperVector(tc
, PC
, NPC
, 2);
562 else if(level
== Hyperprivileged
)
564 doNormalFault(tc
, trapType(), true);
565 getHyperVector(tc
, PC
, NPC
, trapType());
569 doNormalFault(tc
, trapType(), false);
570 getPrivVector(tc
, PC
, NPC
, trapType(), TL
+1);
575 tc
->setNextNPC(NPC
+ sizeof(MachInst
));
578 void PowerOnReset::invoke(ThreadContext
* tc
)
580 //First, enter RED state.
583 //For SPARC, when a system is first started, there is a power
584 //on reset Trap which sets the processor into the following state.
585 //Bits that aren't set aren't defined on startup.
590 tickFields.counter = 0; //The TICK register is unreadable bya
591 tickFields.npt = 1; //The TICK register is unreadable by by !priv
593 softint = 0; // Clear all the soft interrupt bits
594 tick_cmprFields.int_dis = 1; // disable timer compare interrupts
595 tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
596 stickFields.npt = 1; //The TICK register is unreadable by by !priv
597 stick_cmprFields.int_dis = 1; // disable timer compare interrupts
598 stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
601 pstate = 0; // fields 0 but pef
602 pstateFields.pef = 1;
605 hpstateFields.red = 1;
606 hpstateFields.hpriv = 1;
607 hpstateFields.tlz = 0; // this is a guess
608 hintp = 0; // no interrupts pending
609 hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
610 hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
614 #else // !FULL_SYSTEM
616 void SpillNNormal::invoke(ThreadContext
*tc
)
618 doNormalFault(tc
, trapType(), false);
620 Process
*p
= tc
->getProcessPtr();
622 //XXX This will only work in faults from a SparcLiveProcess
623 SparcLiveProcess
*lp
= dynamic_cast<SparcLiveProcess
*>(p
);
626 //Then adjust the PC and NPC
627 Addr spillStart
= lp
->readSpillStart();
628 tc
->setPC(spillStart
);
629 tc
->setNextPC(spillStart
+ sizeof(MachInst
));
630 tc
->setNextNPC(spillStart
+ 2*sizeof(MachInst
));
633 void FillNNormal::invoke(ThreadContext
*tc
)
635 doNormalFault(tc
, trapType(), false);
637 Process
* p
= tc
->getProcessPtr();
639 //XXX This will only work in faults from a SparcLiveProcess
640 SparcLiveProcess
*lp
= dynamic_cast<SparcLiveProcess
*>(p
);
643 //Then adjust the PC and NPC
644 Addr fillStart
= lp
->readFillStart();
645 tc
->setPC(fillStart
);
646 tc
->setNextPC(fillStart
+ sizeof(MachInst
));
647 tc
->setNextNPC(fillStart
+ 2*sizeof(MachInst
));
650 void PageTableFault::invoke(ThreadContext
*tc
)
652 Process
*p
= tc
->getProcessPtr();
654 // address is higher than the stack region or in the current stack region
655 if (vaddr
> p
->stack_base
|| vaddr
> p
->stack_min
)
656 FaultBase::invoke(tc
);
658 // We've accessed the next page
659 if (vaddr
> p
->stack_min
- PageBytes
) {
660 p
->stack_min
-= PageBytes
;
661 if (p
->stack_base
- p
->stack_min
> 8*1024*1024)
662 fatal("Over max stack size for one thread\n");
663 p
->pTable
->allocate(p
->stack_min
, PageBytes
);
664 warn("Increasing stack size by one page.");
666 FaultBase::invoke(tc
);
672 } // namespace SparcISA