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32 #ifndef __ARCH_SPARC_INTERRUPT_HH__
33 #define __ARCH_SPARC_INTERRUPT_HH__
35 #include "arch/sparc/faults.hh"
36 #include "arch/sparc/isa_traits.hh"
37 #include "arch/sparc/registers.hh"
38 #include "cpu/thread_context.hh"
39 #include "debug/Interrupt.hh"
40 #include "params/SparcInterrupts.hh"
41 #include "sim/sim_object.hh"
46 class Interrupts : public SimObject
51 uint64_t interrupts[NumInterruptTypes];
57 setCPU(BaseCPU * _cpu)
62 typedef SparcInterruptsParams Params;
67 return dynamic_cast<const Params *>(_params);
70 Interrupts(Params * p) : SimObject(p), cpu(NULL)
76 InterruptLevel(uint64_t softint)
78 if (softint & 0x10000 || softint & 0x1)
82 while (level > 0 && !(1 << level & softint))
84 if (1 << level & softint)
90 post(int int_num, int index)
92 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
93 assert(int_num >= 0 && int_num < NumInterruptTypes);
94 assert(index >= 0 && index < 64);
96 interrupts[int_num] |= ULL(1) << index;
97 intStatus |= ULL(1) << int_num;
101 clear(int int_num, int index)
103 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
104 assert(int_num >= 0 && int_num < NumInterruptTypes);
105 assert(index >= 0 && index < 64);
107 interrupts[int_num] &= ~(ULL(1) << index);
108 if (!interrupts[int_num])
109 intStatus &= ~(ULL(1) << int_num);
115 for (int i = 0; i < NumInterruptTypes; ++i) {
122 checkInterrupts(ThreadContext *tc) const
128 getInterrupt(ThreadContext *tc)
130 HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
131 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
133 // THESE ARE IN ORDER OF PRIORITY
134 // since there are early returns, and the highest
135 // priority interrupts should get serviced,
136 // it is v. important that new interrupts are inserted
137 // in the right order of processing
140 if (interrupts[IT_HINTP]) {
141 // This will be cleaned by a HINTP write
142 return new HstickMatch;
144 if (interrupts[IT_INT_VEC]) {
145 // this will be cleared by an ASI read (or write)
146 return new InterruptVector;
150 if (interrupts[IT_TRAP_LEVEL_ZERO]) {
151 // this is cleared by deasserting HPSTATE::tlz
152 return new TrapLevelZero;
154 // HStick matches always happen in priv mode (ie doesn't matter)
155 if (interrupts[IT_HINTP]) {
156 return new HstickMatch;
158 if (interrupts[IT_INT_VEC]) {
159 // this will be cleared by an ASI read (or write)
160 return new InterruptVector;
163 if (interrupts[IT_CPU_MONDO]) {
166 if (interrupts[IT_DEV_MONDO]) {
169 if (interrupts[IT_SOFT_INT]) {
170 int level = InterruptLevel(interrupts[IT_SOFT_INT]);
171 return new InterruptLevelN(level);
174 if (interrupts[IT_RES_ERROR]) {
175 return new ResumableError;
177 } // !hpriv && pstate.ie
183 updateIntrInfo(ThreadContext *tc)
189 assert(int_num >= 0 && int_num < NumInterruptTypes);
190 return interrupts[int_num];
194 serialize(std::ostream &os)
196 SERIALIZE_ARRAY(interrupts,NumInterruptTypes);
197 SERIALIZE_SCALAR(intStatus);
201 unserialize(Checkpoint *cp, const std::string §ion)
203 UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes);
204 UNSERIALIZE_SCALAR(intStatus);
207 } // namespace SPARC_ISA
209 #endif // __ARCH_SPARC_INTERRUPT_HH__