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32 #ifndef __ARCH_SPARC_INTERRUPT_HH__
33 #define __ARCH_SPARC_INTERRUPT_HH__
35 #include "arch/sparc/faults.hh"
36 #include "arch/sparc/isa_traits.hh"
37 #include "cpu/thread_context.hh"
47 uint64_t interrupts[NumInterruptTypes];
56 int InterruptLevel(uint64_t softint)
58 if (softint & 0x10000 || softint & 0x1)
62 while (level > 0 && !(1 << level & softint))
64 if (1 << level & softint)
69 void post(int int_num, int index)
71 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
72 assert(int_num >= 0 && int_num < NumInterruptTypes);
73 assert(index >= 0 && index < 64);
75 interrupts[int_num] |= ULL(1) << index;
76 intStatus |= ULL(1) << int_num;
79 void clear(int int_num, int index)
81 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
82 assert(int_num >= 0 && int_num < NumInterruptTypes);
83 assert(index >= 0 && index < 64);
85 interrupts[int_num] &= ~(ULL(1) << index);
86 if (!interrupts[int_num])
87 intStatus &= ~(ULL(1) << int_num);
92 for (int i = 0; i < NumInterruptTypes; ++i) {
98 bool check_interrupts(ThreadContext * tc) const
103 Fault getInterrupt(ThreadContext * tc)
105 int hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
106 int pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
107 bool ie = pstate & PSTATE::ie;
109 // THESE ARE IN ORDER OF PRIORITY
110 // since there are early returns, and the highest
111 // priority interrupts should get serviced,
112 // it is v. important that new interrupts are inserted
113 // in the right order of processing
114 if (hpstate & HPSTATE::hpriv) {
116 if (interrupts[IT_HINTP]) {
117 // This will be cleaned by a HINTP write
118 return new HstickMatch;
120 if (interrupts[IT_INT_VEC]) {
121 // this will be cleared by an ASI read (or write)
122 return new InterruptVector;
126 if (interrupts[IT_TRAP_LEVEL_ZERO]) {
127 // this is cleared by deasserting HPSTATE::tlz
128 return new TrapLevelZero;
130 // HStick matches always happen in priv mode (ie doesn't matter)
131 if (interrupts[IT_HINTP]) {
132 return new HstickMatch;
134 if (interrupts[IT_INT_VEC]) {
135 // this will be cleared by an ASI read (or write)
136 return new InterruptVector;
139 if (interrupts[IT_CPU_MONDO]) {
142 if (interrupts[IT_DEV_MONDO]) {
145 if (interrupts[IT_SOFT_INT]) {
147 InterruptLevelN(InterruptLevel(interrupts[IT_SOFT_INT]));
150 if (interrupts[IT_RES_ERROR]) {
151 return new ResumableError;
158 void updateIntrInfo(ThreadContext * tc)
163 uint64_t get_vec(int int_num)
165 assert(int_num >= 0 && int_num < NumInterruptTypes);
166 return interrupts[int_num];
169 void serialize(std::ostream &os)
171 SERIALIZE_ARRAY(interrupts,NumInterruptTypes);
172 SERIALIZE_SCALAR(intStatus);
175 void unserialize(Checkpoint *cp, const std::string §ion)
177 UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes);
178 UNSERIALIZE_SCALAR(intStatus);
181 } // namespace SPARC_ISA
183 #endif // __ARCH_SPARC_INTERRUPT_HH__