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32 #ifndef __ARCH_SPARC_INTERRUPT_HH__
33 #define __ARCH_SPARC_INTERRUPT_HH__
35 #include "arch/sparc/faults.hh"
36 #include "arch/sparc/isa_traits.hh"
37 #include "cpu/thread_context.hh"
38 #include "params/SparcInterrupts.hh"
39 #include "sim/sim_object.hh"
44 class Interrupts : public SimObject
48 uint64_t interrupts[NumInterruptTypes];
52 typedef SparcInterruptsParams Params;
57 return dynamic_cast<const Params *>(_params);
60 Interrupts(Params * p) : SimObject(p)
66 InterruptLevel(uint64_t softint)
68 if (softint & 0x10000 || softint & 0x1)
72 while (level > 0 && !(1 << level & softint))
74 if (1 << level & softint)
80 post(int int_num, int index)
82 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
83 assert(int_num >= 0 && int_num < NumInterruptTypes);
84 assert(index >= 0 && index < 64);
86 interrupts[int_num] |= ULL(1) << index;
87 intStatus |= ULL(1) << int_num;
91 clear(int int_num, int index)
93 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
94 assert(int_num >= 0 && int_num < NumInterruptTypes);
95 assert(index >= 0 && index < 64);
97 interrupts[int_num] &= ~(ULL(1) << index);
98 if (!interrupts[int_num])
99 intStatus &= ~(ULL(1) << int_num);
105 for (int i = 0; i < NumInterruptTypes; ++i) {
112 checkInterrupts(ThreadContext *tc) const
118 getInterrupt(ThreadContext *tc)
120 int hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
121 int pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
122 bool ie = pstate & PSTATE::ie;
124 // THESE ARE IN ORDER OF PRIORITY
125 // since there are early returns, and the highest
126 // priority interrupts should get serviced,
127 // it is v. important that new interrupts are inserted
128 // in the right order of processing
129 if (hpstate & HPSTATE::hpriv) {
131 if (interrupts[IT_HINTP]) {
132 // This will be cleaned by a HINTP write
133 return new HstickMatch;
135 if (interrupts[IT_INT_VEC]) {
136 // this will be cleared by an ASI read (or write)
137 return new InterruptVector;
141 if (interrupts[IT_TRAP_LEVEL_ZERO]) {
142 // this is cleared by deasserting HPSTATE::tlz
143 return new TrapLevelZero;
145 // HStick matches always happen in priv mode (ie doesn't matter)
146 if (interrupts[IT_HINTP]) {
147 return new HstickMatch;
149 if (interrupts[IT_INT_VEC]) {
150 // this will be cleared by an ASI read (or write)
151 return new InterruptVector;
154 if (interrupts[IT_CPU_MONDO]) {
157 if (interrupts[IT_DEV_MONDO]) {
160 if (interrupts[IT_SOFT_INT]) {
161 int level = InterruptLevel(interrupts[IT_SOFT_INT]);
162 return new InterruptLevelN(level);
165 if (interrupts[IT_RES_ERROR]) {
166 return new ResumableError;
174 updateIntrInfo(ThreadContext *tc)
182 assert(int_num >= 0 && int_num < NumInterruptTypes);
183 return interrupts[int_num];
187 serialize(std::ostream &os)
189 SERIALIZE_ARRAY(interrupts,NumInterruptTypes);
190 SERIALIZE_SCALAR(intStatus);
194 unserialize(Checkpoint *cp, const std::string §ion)
196 UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes);
197 UNSERIALIZE_SCALAR(intStatus);
200 } // namespace SPARC_ISA
202 #endif // __ARCH_SPARC_INTERRUPT_HH__