src/arch/sparc/interrupts.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 #ifndef __ARCH_SPARC_INTERRUPT_HH__
  32 #define __ARCH_SPARC_INTERRUPT_HH__
  33
  34 #include "arch/sparc/faults.hh"
  35 #include "cpu/thread_context.hh"
  36
  37
  38 namespace SparcISA
  39 {
  40     class Interrupts
  41     {
  42       protected:
  43
  44
  45       public:
  46         Interrupts()
  47         {
  48
  49         }
  50         void post(int int_num, int index)
  51         {
  52
  53         }
  54
  55         void clear(int int_num, int index)
  56         {
  57
  58         }
  59
  60         void clear_all()
  61         {
  62
  63         }
  64
  65         bool check_interrupts(ThreadContext * tc) const
  66         {
  67             // so far only handle softint interrupts
  68             int int_level = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT));
  69             if (int_level)
  70                 return true;
  71             else
  72                 return false;
  73         }
  74
  75         Fault getInterrupt(ThreadContext * tc)
  76         {
  77             // conditioning the softint interrups
  78             if (tc->readMiscReg(MISCREG_HPSTATE) & hpriv) {
  79                 // if running in privileged mode, then pend the interrupt
  80                 return NoFault;
  81             } else {
  82                 int int_level = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT));
  83                 if ((int_level <= tc->readMiscReg(MISCREG_PIL)) ||
  84                     !(tc->readMiscReg(MISCREG_PSTATE) & ie)) {
  85                     // if PIL or no interrupt enabled, then pend the interrupt
  86                     return NoFault;
  87                 } else {
  88                     return new InterruptLevelN(int_level);
  89                 }
  90             }
  91         }
  92
  93         void updateIntrInfo(ThreadContext * tc)
  94         {
  95
  96         }
  97
  98         void serialize(std::ostream &os)
  99         {
 100         }
 101
 102         void unserialize(Checkpoint *cp, const std::string &section)
 103         {
 104         }
 105     };
 106 }
 107
 108 #endif // __ARCH_SPARC_INTERRUPT_HH__