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29 #ifndef __ARCH_SPARC_INTERRUPT_HH__
30 #define __ARCH_SPARC_INTERRUPT_HH__
32 #include "arch/sparc/faults.hh"
33 #include "cpu/thread_context.hh"
54 bool interrupts[num_interrupt_types];
60 for (int i = 0; i < num_interrupt_types; ++i) {
61 interrupts[i] = false;
66 void post(int int_type)
68 if (int_type < 0 || int_type >= num_interrupt_types)
69 panic("posting unknown interrupt!\n");
70 if (interrupts[int_type] == false) {
71 interrupts[int_type] = true;
76 void post(int int_num, int index)
81 void clear(int int_num, int index)
91 bool check_interrupts(ThreadContext * tc) const
99 Fault getInterrupt(ThreadContext * tc)
101 int hpstate = tc->readMiscReg(MISCREG_HPSTATE);
102 int pstate = tc->readMiscReg(MISCREG_PSTATE);
103 bool ie = pstate & PSTATE::ie;
105 // THESE ARE IN ORDER OF PRIORITY
106 // since there are early returns, and the highest
107 // priority interrupts should get serviced,
108 // it is v. important that new interrupts are inserted
109 // in the right order of processing
110 if (hpstate & HPSTATE::hpriv) {
112 if (interrupts[hstick_match]) {
113 if (tc->readMiscReg(MISCREG_HINTP) & 1) {
114 interrupts[hstick_match] = false;
116 return new HstickMatch;
119 if (interrupts[interrupt_vector]) {
120 interrupts[interrupt_vector] = false;
122 //HAVEN'T IMPLed THIS YET
126 if (interrupts[hstick_match]) {
132 if (interrupts[trap_level_zero]) {
133 if ((pstate & HPSTATE::tlz) && (tc->readMiscReg(MISCREG_TL) == 0)) {
134 interrupts[trap_level_zero] = false;
136 return new TrapLevelZero;
139 if (interrupts[hstick_match]) {
140 if (tc->readMiscReg(MISCREG_HINTP) & 1) {
141 interrupts[hstick_match] = false;
143 return new HstickMatch;
147 if (interrupts[cpu_mondo]) {
148 interrupts[cpu_mondo] = false;
152 if (interrupts[dev_mondo]) {
153 interrupts[dev_mondo] = false;
157 if (interrupts[soft_interrupt]) {
158 int il = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT));
159 // it seems that interrupt vectors are right in
160 // the middle of interrupt levels with regard to
161 // priority, so have to check
163 interrupts[interrupt_vector]) {
164 // may require more details here since there
165 // may be lots of interrupts embedded in an
166 // platform interrupt vector
167 interrupts[interrupt_vector] = false;
172 if (il > tc->readMiscReg(MISCREG_PIL)) {
173 uint64_t si = tc->readMiscReg(MISCREG_SOFTINT);
174 uint64_t more = si & ~(1 << (il + 1));
175 if (!InterruptLevel(more)) {
176 interrupts[soft_interrupt] = false;
179 return new InterruptLevelN(il);
183 if (interrupts[resumable_error]) {
184 interrupts[resumable_error] = false;
186 return new ResumableError;
193 void updateIntrInfo(ThreadContext * tc)
198 void serialize(std::ostream &os)
200 SERIALIZE_ARRAY(interrupts,num_interrupt_types);
201 SERIALIZE_SCALAR(numPosted);
204 void unserialize(Checkpoint *cp, const std::string §ion)
206 UNSERIALIZE_ARRAY(interrupts,num_interrupt_types);
207 UNSERIALIZE_SCALAR(numPosted);
210 } // namespace SPARC_ISA
212 #endif // __ARCH_SPARC_INTERRUPT_HH__